Semiconductors, from the transistor to the AI accelerator

Semiconductor physics

Why silicon can be switched between conducting and insulating, and how adding a few impurity atoms per million controls it.

1.1Bands and the band gap

In a crystal, the energy levels of billions of atoms merge into bands. Electrons in the filled valence band cannot carry current; electrons lifted into the empty conduction band can. The energy gap between the two decides the material's character: metals have no gap, insulators such as SiO₂ have a gap of about 9 eV, and silicon sits in between at 1.12 eV at room temperature.

Heat lifts a few electrons across the gap, leaving behind holes, missing electrons that behave like positive charges. Pure silicon at 300 K has only about 10¹⁰ free electrons per cm³, against roughly 5×10²² atoms per cm³, so it conducts poorly.

1.2Doping

Replacing a tiny fraction of silicon atoms with impurities changes everything. Phosphorus or arsenic (group V) has one extra electron that is easily freed: a donor, giving n-type silicon. Boron (group III) has one electron too few and creates a hole: an acceptor, giving p-type silicon. A doping of 10¹⁶ cm⁻³ — one impurity per five million atoms — raises the carrier density a million-fold.

1.3The pn junction

Where p-type meets n-type silicon, electrons and holes diffuse across and recombine, leaving a thin depletion region of fixed charge with a built-in voltage of about 0.6–0.8 V. Forward bias shrinks the barrier and current rises exponentially; reverse bias widens it and almost no current flows. This one-way behaviour is a diode.

The MOSFET

The metal–oxide–semiconductor field-effect transistor: a voltage-controlled switch, and the building block of every digital chip.

2.1A switch made of fields

An n-channel MOSFET has an n-type source and drain in p-type silicon, with a gate electrode separated from the channel by a few nanometres of insulator. A positive gate voltage pulls electrons to the surface; above the threshold voltage V_t they form a conducting channel between source and drain. A p-channel device works the same way with opposite polarities. The gate draws almost no DC current, which is why CMOS logic can be so efficient.

2.2Operating regions

• Cutoff (V_GS < V_t): ideally off, in practice a small subthreshold leakage flows.
• Linear (small V_DS): the channel acts like a resistor controlled by the gate.
• Saturation (V_DS ≥ V_GS − V_t): current is set mainly by the gate voltage.

In nanometre transistors, carriers hit a maximum velocity, so current grows more nearly linearly with gate overdrive than the square law suggests. Designers use detailed compact models (BSIM-CMG for FinFETs and GAA) from the foundry PDK rather than this formula.

2.3Leakage and the 60 mV/decade limit

Below threshold, current falls exponentially with gate voltage. The subthreshold swing S is the gate-voltage change for a tenfold change in current. Thermal physics sets a floor of S = ln(10)·kT/q ≈ 60 mV/decade at room temperature. With a 0.7 V supply and a 0.3 V threshold, a perfect switch gives at most about 10⁶–10⁷ between on and off current; real devices with S = 70–80 mV/decade give less.

2.4Scaling, and why it changed

From the 1970s to the mid-2000s, Dennard scaling shrank dimensions and voltage together by the same factor, so each generation was faster at constant power density. Because the threshold voltage cannot drop much without leakage exploding, supply voltages stalled near 0.7–1.0 V around 2005. Since then, gains have come from new structures (strained silicon, high-k metal gates, FinFETs, gate-all-around), multicore and specialised accelerators, rather than higher clock speeds.

CMOS logic and power

How pairs of n- and p-type transistors build logic that draws almost no current when idle, and where the power goes when it switches.

3.1The inverter

A CMOS inverter puts a pMOS from the supply to the output and an nMOS from the output to ground, with both gates tied to the input. Input high turns the nMOS on and the pMOS off, pulling the output low; input low does the opposite. In either steady state one transistor is off, so no current flows from supply to ground.

3.2Gates from networks

Any static CMOS gate has an nMOS pull-down network and a complementary pMOS pull-up network. Transistors in series in one network appear in parallel in the other. A two-input NAND has two nMOS in series and two pMOS in parallel; NAND and NOR are each universal, and standard-cell libraries contain hundreds of variants of such gates in different sizes.

3.3Where the power goes

Every time a node switches, its capacitance is charged from the supply and later discharged to ground.

α is the activity factor (fraction of nodes switching per cycle), C the switched capacitance and f the clock frequency. Because power scales with V², a 10% voltage cut saves about 19% of dynamic power — the reason chips change voltage with load (DVFS).

3.4Saving power

• Clock gating stops the clock to idle blocks, cutting α.
• Power gating switches off idle blocks entirely, cutting leakage.
• DVFS lowers voltage and frequency together when full speed is not needed.
• Multiple threshold voltages: fast low-V_t cells only on critical paths, low-leakage high-V_t cells elsewhere.

Digital design and RTL

How engineers describe hardware in code: registers, combinational logic, state machines and pipelines.

4.1Registers and logic

Synchronous digital design alternates two ingredients: combinational logic (gates whose outputs depend only on current inputs) and registers (flip-flops that capture values on a clock edge). Data moves from register to register once per clock cycle; this register-transfer view is what RTL means.

module counter #(parameter W = 8) (
  input  logic         clk, rst_n, en,
  output logic [W-1:0] q
);
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n)  q <= '0;        // asynchronous reset
    else if (en) q <= q + 1'b1;  // register update on the clock edge
endmodule

4.2State machines

A finite-state machine stores its state in registers and computes the next state and outputs in combinational logic. Controllers for buses, memory interfaces and protocols are FSMs. Encoding choices (binary, one-hot) trade register count against logic depth.

4.3Pipelining

Splitting a long computation into stages separated by registers lets a new input enter every cycle. Latency (cycles from input to output) rises slightly, but throughput rises by roughly the number of stages, and each stage is short enough for a faster clock. Hazards — a later stage needing a result not yet produced — are handled with forwarding, stalls or careful scheduling.

4.4Crossing clock domains

Large chips have many clocks. A signal passing between unrelated clocks can be sampled mid-transition and leave a flip-flop metastable. Single bits cross through two- or three-flip-flop synchronisers; multi-bit data uses asynchronous FIFOs with Gray-coded pointers. CDC errors are a classic source of silicon bugs, so dedicated tools check them.

Synthesis and static timing

How RTL becomes a netlist of gates, and how engineers prove every path meets the clock.

5.1Logic synthesis

A synthesis tool reads RTL plus constraints (clock periods, input and output delays, in SDC format) and maps the design onto standard cells from the foundry library, choosing cell types and sizes to meet timing at minimum area and power. The result is a gate-level netlist.

5.2Setup and hold

Static timing analysis (STA) checks every register-to-register path without simulation. Data launched at one clock edge must arrive before the next edge minus the capture flip-flop's setup time, and must not change too soon after the edge (hold).

5.3Corners and variation

Transistor speed varies with manufacturing (process), voltage and temperature. Sign-off checks setup at slow corners (slow process, low voltage, worst temperature) and hold at fast corners, often across dozens of combinations, with extra margins for on-chip variation and aging. At advanced nodes, wire resistance and voltage drop are as important as gate delay.

5.4Closing timing

When paths fail, engineers upsize cells, swap to faster threshold flavours, restructure logic, add pipeline stages, or move blocks closer together in the layout. Hold violations are fixed by inserting delay buffers. Timing closure is iterative and often the longest phase before tape-out.

Physical design

Turning a netlist into geometry: floorplanning, placement, clock trees, routing and the checks that guarantee it can be manufactured.

6.1Floorplan and power grid

The floorplan fixes the die size, places large blocks (memories, analog, I/O) and plans the power-delivery network: a mesh of wide wires on the top metal layers feeding every cell. Since Intel 18A and TSMC A16 the power network can sit on the back of the wafer instead, freeing front-side wires for signals.

6.2Placement, clocks and routing

• Placement positions millions or billions of standard cells in rows, minimising wire length and congestion while meeting timing.
• Clock-tree synthesis builds a balanced buffer tree (or mesh) that delivers the clock to every flip-flop with controlled skew; the clock network can use a large share of dynamic power.
• Routing connects every net through a stack of a dozen or more metal layers — very fine at the bottom for local wiring, thick at the top for long-distance and power.

6.3Power integrity and reliability

Current flowing through resistive wires causes IR drop: cells far from a supply bump see a lower voltage and run slower. High current density also makes metal atoms migrate over years (electromigration), eventually opening or shorting wires. Both are analysed with dedicated tools and fixed by widening wires and adding vias.

6.4Physical verification

DRC (design-rule check) confirms every shape obeys the foundry's thousands of spacing, width and density rules. LVS (layout versus schematic) confirms the drawn layout implements exactly the intended circuit. Only a clean design can be taped out.

Memory

SRAM, DRAM, HBM and flash: the memories every processor depends on, and why moving data now costs more than computing on it.

7.1SRAM

A static RAM cell uses six transistors: two cross-coupled inverters that hold a bit, plus two access transistors connected to the bit lines. It is fast and needs no refresh, but is large; caches and register files are SRAM. Its area stopped shrinking for two generations (N5 and N3E both use a 0.021 µm² cell) before TSMC N2 reached about 0.0175 µm².

7.2DRAM

A DRAM cell is one transistor and one tiny capacitor. The charge leaks away, so every row must be refreshed, typically within 64 ms. Reading is destructive and slower than SRAM, but density is far higher, which is why main memory is DRAM.

7.3HBM and flash

HBM stacks 8–16 DRAM dies connected by through-silicon vias on a base die, with a 1,024-bit (HBM3E) or 2,048-bit (HBM4) interface placed beside the processor on an interposer. NAND flash stores charge in cells stacked in hundreds of layers; it keeps data without power and is used for storage, not working memory.

7.4The memory wall

Processor compute has grown far faster than memory bandwidth. Moving a 32-bit word from off-chip DRAM costs on the order of a hundred times the energy of a 32-bit arithmetic operation, so modern designs keep data close: larger on-chip SRAM, HBM next to the compute die, and data reuse in the algorithm. Module 10 quantifies this with the roofline model.

Fabrication

How a design becomes silicon: the process steps, the cleanroom, and why yield decides cost.

8.1The process loop

A 300 mm wafer goes through a repeated loop several dozen times: deposit a film (CVD, ALD, sputtering), pattern it with photolithography, etch away what is not protected, implant or anneal to change electrical properties, polish flat (CMP) and clean. A leading-edge chip needs on the order of a thousand steps and roughly three months in the fab.

8.2Front end and back end

The front end of line builds the transistors in the silicon — for GAA nodes this includes growing alternating Si/SiGe layers and later removing the SiGe to release the nanosheets. The back end of line builds the copper interconnect stack above them, layer by layer, insulated by low-k dielectrics.

8.3Lithography

A scanner projects the mask pattern onto light-sensitive resist, shrunk four times. Resolution follows CD = k₁·λ/NA: 193 nm immersion DUV for most layers, 13.5 nm EUV for the finest, and High-NA EUV (NA 0.55) arriving for the next nodes. Features below a single exposure's limit use multiple patterning, at extra cost per layer.

8.4Yield

Random particles and defects kill dies. With defect density D₀ and die area A, the Poisson model gives yield Y = e^(−A·D₀). At D₀ = 0.1 cm⁻², a 1 cm² die yields about 90%, an 8 cm² die only about 45%. The main guide's yield and cost calculator shows how chiplets change this.

Packaging and chiplets

How dies connect to the world and to each other — the part of chip design that has changed most in the past five years.

9.1From wire bonds to flip chip

Older packages connected the die edge to the package with fine gold wires. High-performance chips are flipped upside down and connected through thousands of solder bumps across their whole area, giving far more I/O and better power delivery.

9.22.5D and 3D

• 2.5D: several dies sit side by side on a silicon interposer or bridge with dense wiring (TSMC CoWoS, Intel EMIB). This is how GPUs sit next to HBM stacks.
• 3D: dies are stacked and bonded face to face, with copper-to-copper hybrid bonding at micrometre pitch (TSMC SoIC, Intel Foveros), giving the shortest, lowest-energy connections.

9.3Why chiplets

Splitting a design into chiplets lets each part use the right process (logic on 2 nm, I/O on an older node), improves yield because each die is smaller, allows designs larger than one reticle, and enables reuse across products. The costs are die-to-die interfaces (standardised by UCIe), packaging complexity and the need for known-good-die testing, since one bad chiplet scraps the whole package.

9.4Heat

Accelerators now dissipate over a kilowatt per package. Stacking dies traps heat inside, so thermal design — liquid cold plates today, possibly microfluidic channels in the silicon tomorrow — is part of the architecture decision, not an afterthought.

AI accelerator architecture

Why GPUs and TPUs look the way they do: matrix engines, low-precision number formats, and the balance between compute and memory.

10.1Matrix multiply everywhere

Neural networks spend most of their arithmetic in matrix multiplications. Multiplying an M×K by a K×N matrix needs 2·M·K·N operations but only reads M·K + K·N values, so there is a lot of reuse — if the hardware can exploit it.

10.2Matrix engines

A systolic array (used in Google's TPUs) is a grid of multiply–accumulate units through which operands flow in step, each value reused many times without returning to memory. GPU tensor cores perform small matrix multiplications per instruction across thousands of cores. Both trade flexibility for arithmetic density.

10.3Fewer bits per number

Halving the bits per number roughly doubles the operations per second and halves the memory traffic. Training moved from FP32 to BF16 and FP8; inference now uses 4-bit formats such as NVFP4 and MXFP4, which share a scale factor across small blocks of values to keep accuracy. NVIDIA quotes Rubin at 50 PFLOPS in NVFP4.

10.4The roofline model

A kernel's arithmetic intensity I is operations per byte moved from memory. Attainable performance is limited by whichever is lower: peak compute, or memory bandwidth × I.

Verification and test

Proving the design is right before tape-out, and proving each manufactured die works after.

11.1Verification

Verification usually takes more engineering effort than design. Simulation with constrained-random UVM testbenches exercises the RTL; coverage metrics show which behaviours have been tested. Formal verification proves properties mathematically for all inputs, ideal for control logic and protocols. Emulation and FPGA prototypes run the design millions of times faster than simulation so real software can boot before silicon exists.

11.2Why it matters

A leading-edge mask set costs tens of millions of dollars and a respin adds months. Industry surveys, such as the Wilson Research Group functional verification study, report that only a minority of projects achieve working first silicon, with logic and functional bugs the leading cause.

11.3Manufacturing test

Verification asks whether the design is correct; test asks whether each manufactured die matches the design. Scan chains link the flip-flops into shift registers so testers can load and read internal state. ATPG (automatic test pattern generation) creates patterns to detect modelled faults such as stuck-at-0/1 and slow transitions. Memories carry built-in self-test (MBIST) with spare rows and columns for repair.

11.4Silicon bring-up

When first silicon returns, teams run tests on the tester and on boards, characterise speed and power across voltage and temperature, and debug failures with on-chip monitors and trace. Results feed back into the next stepping and into the yield-learning loop with the foundry.

Analog and data converters

Every chip that touches the real world — radios, sensors, audio, memory interfaces — needs analog circuits and converters between continuous signals and bits.

12.1The transistor as an amplifier

In analog circuits a transistor is biased in saturation and small input changes are amplified. Its transconductance g_m converts voltage to current, and its output resistance r_o sets the intrinsic gain g_m·r_o. Short modern transistors have low r_o and low supply voltages, so intrinsic gain and signal swing shrink with each node. That is why analog blocks barely shrink and are often moved to older nodes or separate chiplets.

12.2Data converters

• SAR ADC: a binary search with a capacitor DAC; very efficient at 8–16 bits and up to hundreds of MS/s.
• Pipeline ADC: resolves a few bits per stage for high speed.
• Delta-sigma ADC: oversamples and shapes noise out of band for 16–24 bits at audio and sensor rates.
• Flash ADC: 2ᴺ−1 comparators in parallel; the fastest but limited to a few bits.

12.3Clocks and PLLs

A phase-locked loop multiplies a clean reference (often a 25–100 MHz crystal) up to GHz clocks. A phase detector compares the divided output with the reference and steers a voltage-controlled oscillator. The clock's timing noise, jitter, eats into the timing budget of digital logic and the SNR of fast converters and SerDes.

12.4References and regulators

A bandgap reference combines two voltages with opposite temperature trends to produce about 1.2 V that barely drifts with temperature. Low-dropout regulators (LDOs) give clean local supplies for sensitive blocks. Analog layout uses matching, symmetry and guard rings, and still relies heavily on expert hand design, although AI-assisted sizing is an active research area.

High-speed I/O and SerDes

How chips push hundreds of gigabits per second over copper and fibre — the links between GPUs, switches and memory.

13.1Serial links

A SerDes turns wide parallel data into one very fast serial lane and back, embedding the clock in the data so the receiver recovers it (clock and data recovery). PCIe, Ethernet, NVLink, UCIe and DRAM interfaces are all built from such lanes. A modern switch chip has hundreds of them.

13.2NRZ and PAM4

NRZ sends one bit per symbol with two levels. PAM4 uses four levels to send two bits per symbol, doubling the data rate at the same symbol rate, but each eye is one third the height — about a 9.5 dB SNR penalty — so PAM4 links need forward error correction. 112 Gb/s and 224 Gb/s per lane links are PAM4, at roughly 56 and 112 GBaud.

13.3Equalisation

Copper traces lose more signal at high frequency, smearing each symbol into its neighbours. Transmitters pre-emphasise edges (FFE); receivers boost high frequencies (CTLE) and cancel the tail of previous symbols with a decision-feedback equaliser (DFE). Many 112G+ receivers sample with fast ADCs and equalise digitally (DSP-based SerDes).

13.4Copper runs out of reach

As rates double, usable copper distance shrinks. That is why NVIDIA's racks use dense copper spines only inside the rack, and why switch makers are moving optics into the package (co-packaged optics, TSMC COUPE) to cut the power spent driving electrical signals to the front panel.

Power delivery

Feeding hundreds of amperes at under a volt to a chip, without the voltage sagging when the load jumps.

14.1From the wall to the core

Power arrives as AC or high-voltage DC, is converted to 48–54 V in the rack, then to ~12 V or directly to the core voltage of about 0.7–0.9 V by voltage-regulator modules beside the package. A 1 kW accelerator at 0.75 V draws over 1,300 A, so even micro-ohms of resistance waste watts and drop voltage.

14.2Target impedance

Logic can tolerate only a few percent of supply variation. The power-delivery network (PDN) — regulators, board, package, on-die grid and capacitors — must look like a very low impedance across a wide frequency range.

14.3Decoupling capacitors

Regulators react in microseconds; logic switches in picoseconds. Capacitors in between supply the charge for fast transients: bulk capacitors on the board, ceramic capacitors under the package, and deep-trench or MIM capacitors in the interposer and on the die for the fastest edges.

14.4Regulators closer to the die

Moving the last conversion stage into the package or onto the die (integrated voltage regulators) shortens the high-current path and lets each core change voltage in nanoseconds. Backside power delivery (PowerVia, Super Power Rail) shortens the last millimetres too. Rack-level 800 V DC distribution (main guide, Power section) attacks the same problem at the building scale.

Thermal design

Every watt that goes in comes out as heat. How hot the transistors get decides speed, reliability and how many chips fit in a rack.

15.1Thermal resistance

Heat flows from the transistors (junction) through the die, thermal interface material, lid and heat sink to the air or coolant. Each layer has a thermal resistance θ in °C per watt; like resistors in series, they add up.

15.2Hotspots and heat flux

Power is not uniform: matrix engines and SerDes can run far hotter than caches. Average heat flux on large accelerators is on the order of 100 W/cm², with local hotspots several times higher. Stacking dies (HBM, SoIC) adds layers that heat must cross.

15.3Cooling options

• Air: heat sinks and fans; simple, limited to several hundred watts per package.
• Direct liquid cooling: cold plates on the package; standard for GB200/GB300/Rubin racks.
• Immersion: boards submerged in dielectric fluid, single- or two-phase.
• In-silicon microfluidics: coolant channels etched into the die (research and early prototypes).

15.4Throttling and leakage

Leakage rises steeply with temperature, which heats the chip further. On-die thermal sensors let firmware lower voltage and frequency before the maximum junction temperature (typically about 100–110 °C) is reached. Running cooler therefore gives both more performance per watt and longer life.

Reliability and aging

Chips must work for years — fifteen or more in cars — while their wires and transistors slowly degrade, and cosmic rays flip bits.

16.1Wear-out

• Electromigration: current pushes metal atoms, eventually opening wires (Black's equation: lifetime falls with current density and temperature).
• Bias temperature instability (BTI): threshold voltage drifts under gate stress, slowing transistors over years.
• Hot-carrier injection: energetic carriers damage the gate insulator.
• Dielectric breakdown (TDDB): the gate or inter-metal insulator eventually fails under field.

Designers add timing guardbands for end-of-life speed and size wires for current. Reliability is qualified by stressing parts at high temperature and voltage and extrapolating.

16.2Soft errors

Neutrons from cosmic rays and alpha particles from packaging materials can flip a stored bit without damaging the chip. Memories use error-correcting codes (SECDED corrects one bit and detects two per word); critical logic uses parity, redundancy or hardened flip-flops. Failure rates are quoted in FIT: failures per 10⁹ device-hours.

16.3Silent data corruption

At hyperscale, a small fraction of CPUs compute wrong answers without any error being reported. Google ("Cores that don't count", 2021) and Meta ("Silent Data Corruptions at Scale", 2021) described such mercurial cores across large fleets. Operators now run in-field test suites and retire suspect parts; AI training clusters with tens of thousands of accelerators are especially exposed.

16.4Standards

Automotive chips qualify to AEC-Q100 and design to ISO 26262 functional safety, with redundancy, built-in self-test at start-up and lifetimes of 15+ years. Data-centre chips trade some lifetime for performance, often with five- to seven-year service targets.

Processor architecture

How CPUs extract performance from a single instruction stream, and why parallelism has limits.

17.1ISA and microarchitecture

The instruction-set architecture (x86-64, Arm v9, RISC-V RVA23) is the contract with software. The microarchitecture is how a particular chip implements it: Apple, Qualcomm and Arm all build very different cores for the same Arm ISA.

17.2Doing more per cycle

Modern cores fetch and decode several instructions per cycle (superscalar), predict branches with over 95% accuracy, execute instructions out of order as their inputs become ready, and retire them in order so software sees a consistent result. Wide cores issue eight or more instructions per cycle but spend much of their area on prediction, renaming and reordering.

17.3Caches

With many cores, coherence protocols keep caches consistent, and 3D-stacked cache (for example AMD's V-Cache) adds capacity without enlarging the core die.

17.4Amdahl's law

Hardware security

Attacks that exploit the physics and microarchitecture of chips, and the hardware features that defend against them.

18.1Side channels

A chip leaks information through timing, power draw and electromagnetic emissions. Measuring the power of a smart card during encryption can reveal its key (differential power analysis). Defences include constant-time code, masking and noise generation — the same concern raised for post-quantum cryptography implementations.

18.2Speculation and memory attacks

Spectre and Meltdown (2018) showed that speculative, out-of-order execution can leave secret-dependent traces in caches. Rowhammer showed that repeatedly accessing DRAM rows can flip bits in neighbouring rows. Mitigations span microcode, compilers, operating systems and new hardware such as target-row refresh.

18.3Roots of trust

A hardware root of trust holds keys in fused or protected storage and verifies each stage of firmware at start-up (secure boot). Trusted execution environments — Arm TrustZone, Intel TDX, AMD SEV — and confidential computing on recent data-centre GPUs encrypt data in use so even the host cannot read it.

18.4Supply-chain risks

The chip business

Who designs, who manufactures, what it costs, and why volume decides everything.

19.1Business models

• Fabless companies design chips and outsource manufacturing (NVIDIA, AMD, Apple, Qualcomm, MediaTek, Broadcom).
• Foundries manufacture for others (TSMC, Samsung Foundry, GlobalFoundries, UMC, SMIC, Intel Foundry).
• IDMs design and manufacture their own (Intel, Samsung, Texas Instruments, many analog and power companies).
• OSATs assemble and test (ASE, Amkor, JCET), though advanced packaging is increasingly done by foundries.

19.2Tools and IP

Three companies — Synopsys, Cadence and Siemens EDA — supply most design software. Designs reuse licensed IP blocks: CPU cores (Arm, RISC-V vendors), interfaces (PCIe, DDR, UCIe PHYs), memories and analog blocks. A modern SoC can contain hundreds of IP blocks from dozens of suppliers.

19.3NRE and volume

Non-recurring engineering (NRE) — design teams, tools, IP licences, masks, prototypes — runs to hundreds of millions of dollars for a leading-edge chip, while each additional chip costs only silicon, packaging and test. The cost per chip therefore falls sharply with volume.

19.4A project timeline

A large chip typically takes two to four years from specification to volume: architecture and RTL (a year or more), verification in parallel, physical design and sign-off (six to twelve months), tape-out, three months of fabrication, bring-up and qualification. Many companies now run several generations in parallel to ship yearly.

Beyond CMOS

Technologies that may extend or complement silicon logic, and how close each is to products.

20.1Extending the transistor

Complementary FETs stack nMOS on pMOS to roughly halve cell area; imec places them around the A7 node (~2033). Atom-thin 2D channels such as MoS₂ keep gate control at extreme lengths; a 5,900-transistor RISC-V processor in MoS₂ was reported in Nature in 2025.

20.2New memories

MRAM stores bits in magnetic orientation and is already offered as embedded non-volatile memory at 28–22 nm-class nodes. ReRAM and phase-change memory change resistance; ferroelectric memories (FeRAM, FeFET) use polarisation. They compete for embedded storage and for computing inside memory arrays.

20.3New computing styles

• Photonic computing: matrix operations with light; Nature (2025) reported a photonic processor running ResNet and BERT.
• Neuromorphic: event-driven, brain-inspired chips such as Intel's Loihi 2 and IBM's NorthPole.
• In-memory and analog computing: multiply–accumulate inside memory arrays to avoid data movement.
• Quantum processors: superconducting and spin qubits are made with semiconductor fabrication tools and cryogenic CMOS control chips.

20.4How to judge a claim

Ask what was demonstrated (single device, circuit or system), at what scale, against which baseline, and whether it can be made in a high-volume fab. The main guide's Research section tracks these results.

Masks and computational lithography

Printing a 20 nm feature with 13.5 nm light takes heavy computation on the mask and a fight against the randomness of photons.

21.1Photomasks

A mask carries the pattern of one layer at four times final size. DUV masks are chrome on quartz and transmit light; EUV masks are reflective — a stack of about 40 molybdenum–silicon layer pairs with an absorber on top — because no material is transparent at 13.5 nm. A thin membrane, the pellicle, keeps particles off the mask during exposure.

21.2Optical proximity correction

Features near the resolution limit do not print as drawn: corners round off, line ends pull back and dense and isolated lines print differently. OPC pre-distorts the mask with serifs, biases and assist features so the printed result matches the design. Inverse lithography (ILT) computes the ideal, often curvilinear, mask shape directly; it is so computationally heavy that GPU acceleration (for example NVIDIA cuLitho) is now used in production flows.

21.3Stochastic effects

An EUV photon carries about 92 eV, 14 times more than a 193 nm DUV photon, so the same dose delivers 14 times fewer photons. At small dimensions the random number of photons and resist molecules in each spot causes line-edge roughness, missing contacts and bridges — stochastic defects. Raising the dose reduces the noise but lowers scanner throughput.

21.4The trade-off

Lithography cost is set by scanner throughput (wafers per hour) and the number of exposures per layer. Higher dose, multiple patterning and High-NA each cost money; resists with better sensitivity, metal-oxide resists and dry resists are research directions to get more signal per photon.

Metrology and yield learning

You cannot control what you cannot measure: how fabs check nanometre features on every wafer and turn the data into higher yield.

22.1Measuring the invisible

• CD-SEM: electron microscopes measure critical dimensions of printed lines.
• Optical critical-dimension (scatterometry): fits light reflected from test gratings to models — fast and non-destructive.
• Defect inspection: optical and e-beam tools scan wafers for particles and pattern defects.
• TEM cross-sections: slices of sample wafers reveal the 3D structure of GAA devices, at the cost of destroying the sample.

22.2Overlay

Each layer must land on the previous one within a nanometre or two. Overlay error comes from the scanner, the wafer stage, wafer distortion, the mask and metrology itself; independent contributions combine as the root sum of squares.

22.3Statistical process control

Every tool and step is monitored with control charts. A measurement outside the control limits, or a trend such as several points drifting one way, stops the tool or holds the lot before bad wafers pile up. Advanced process control feeds measurements forward and back to adjust the next exposure or etch automatically.

22.4Yield learning

Electrical test results are mapped back to wafer position, process tool and design pattern. Systematic failures (a pattern that prints badly, a tool that drifts) are found by correlating these data; random defects are tracked as defect density. New nodes ramp from low initial yield to mature yield over months to years, and the speed of that ramp is a major competitive advantage of leading foundries.

GPU architecture

How a GPU runs tens of thousands of threads at once, and the hardware limits that decide how fast a kernel runs.

23.1SMs, warps and SIMT

An NVIDIA GPU is built from streaming multiprocessors (SMs); a large data-centre GPU has well over a hundred. Each SM runs threads in groups of 32 called warps, all executing the same instruction on different data (single instruction, multiple threads). Branches that send threads in a warp different ways are executed one after another (divergence), wasting lanes.

23.2Hiding latency

A global-memory access takes hundreds of cycles. Instead of large caches and out-of-order logic, a GPU keeps many warps resident and switches to another warp each cycle while others wait. The fraction of the maximum resident warps actually present is occupancy. It is limited by registers per thread, shared memory per block and threads per block.

23.3The memory hierarchy

Registers (fastest, per thread), shared memory and L1 (per SM, programmer-managed), L2 (shared, tens of MB) and HBM (hundreds of GB at several TB/s). Global loads are fastest when the 32 threads of a warp read consecutive addresses, so the hardware merges them into few transactions (coalescing). Tiling a matrix multiply into shared memory turns repeated HBM reads into fast on-chip reuse.

23.4Tensor cores and asynchronous copies

Tensor cores perform small matrix multiply–accumulates per instruction in FP16, BF16, FP8 and FP4 and deliver most of a modern GPU's FLOPS. Recent architectures add asynchronous bulk copies between HBM and shared memory (the Tensor Memory Accelerator) so loading the next tile overlaps computing the current one. Kernel libraries such as CUTLASS and compilers such as Triton exist to orchestrate these features — see the guide's GPU optimization section.

AI cluster networking

Training a frontier model spreads one computation over thousands of accelerators; the network between them is part of the computer.

24.1Scale-up and scale-out

Scale-up links a group of accelerators with very high bandwidth and memory semantics: NVLink connects 72 GPUs in a Vera Rubin NVL72 rack at 3.6 TB/s per GPU. Scale-out connects racks with InfiniBand or Ethernet NICs at 400–800 Gb/s per port. Parallel strategies are mapped so the heaviest traffic (tensor parallelism) stays inside the scale-up domain.

24.2Collectives

Data-parallel training ends each step with an all-reduce that sums gradients across all workers. Other collectives — all-gather, reduce-scatter, all-to-all for mixture-of-experts — move activations and parameters. Libraries such as NCCL choose ring or tree algorithms for the topology.

24.3Topologies

Fat-tree (Clos) networks give full bisection bandwidth between any pair of nodes using layers of switches; rail-optimised designs connect GPU k of every server to the same switch. Switch chips with 100+ Tb/s of capacity and co-packaged optics are being built for these networks.

24.4Failures at scale

With tens of thousands of GPUs, links and nodes fail daily. Training frameworks checkpoint frequently, detect slow or faulty nodes and restart around them; the time lost to failures and restarts is a significant share of total cost.

FPGAs and reconfigurable computing

Chips you can rewire after manufacture — and when they beat both CPUs and custom ASICs.

25.1Inside an FPGA

A field-programmable gate array is a grid of look-up tables (small memories that implement any function of about six inputs), flip-flops, DSP slices (hard multipliers–accumulators), block RAM, and a programmable routing network, surrounded by high-speed transceivers. Modern devices add hard CPU cores, AI engines and even HBM.

25.2Design flow

RTL (or C++ through high-level synthesis) is synthesised to LUTs, placed and routed onto the device, and compiled into a bitstream that configures it in milliseconds. A design can be changed and reloaded in the field, which is impossible for an ASIC.

25.3When to use which

25.4Where FPGAs win

Low-volume or fast-changing products, ultra-low-latency trading, network packet processing, telecom radio units, aerospace and defence, test equipment — and prototyping ASICs before tape-out, where large FPGA boards emulate a design so its software can be developed early (Module 11).

RF and wireless chips

The radios in phones, base stations and satellites, and why they use different semiconductors from digital logic.

26.1The transceiver chain

Receive: antenna → filter → low-noise amplifier → mixer (down to baseband using a PLL local oscillator) → ADC. Transmit: DAC → mixer up to RF → power amplifier → antenna. The LNA's noise figure sets sensitivity; the PA's efficiency dominates a phone's radio power budget.

26.2Link budget

26.3mmWave and beamforming

5G mmWave bands (around 24–52 GHz) offer wide channels but suffer high path loss and blockage. Phased-array modules with many small antennas adjust phase per element to steer beams, integrating dozens of transceiver channels in one package.

26.4Materials for RF

• RF-SOI CMOS: antenna switches and front-end modules in nearly every phone.
• SiGe BiCMOS: fast bipolar transistors for mmWave and automotive radar.
• GaAs: phone power amplifiers.
• GaN on SiC: high-power base-station and radar amplifiers.
• Acoustic filters (BAW, SAW) separate the many bands a phone supports.

Power and compound semiconductors

Wide-band-gap materials that switch hundreds of volts efficiently, in electric cars, chargers, solar inverters and data centres.

27.1What a power device must do

A power switch must block a high voltage when off, carry large current with little loss when on, and switch quickly. A wider band gap gives a higher critical electric field, so a thinner, more heavily doped drift layer can block the same voltage — lowering on-resistance and allowing higher switching frequencies with smaller magnetics.

27.2Device types

Silicon power MOSFETs dominate below a few hundred volts; silicon IGBTs combine MOS control with bipolar conduction for high-current, high-voltage switching. SiC MOSFETs replace IGBTs in many 800 V electric-vehicle inverters, extending range through lower losses. GaN HEMTs use a two-dimensional electron gas at an AlGaN/GaN interface for very fast switching.

27.3Manufacturing differences

SiC wafers are grown from vapour at over 2,000 °C, are hard to make without defects and have only recently moved from 150 mm to 200 mm. GaN is mostly grown as a thin layer on silicon or SiC substrates. Power devices use older, cheaper process nodes; their value is in materials, voltage rating and packaging that removes heat.

27.4Why it matters for computing

The same devices sit in the power path of AI data centres: 800 V DC distribution and solid-state transformers (main guide, Power section) depend on SiC and GaN switches, and every percent of conversion efficiency is megawatts at campus scale.

DTCO and standard cells

Why density now comes as much from cell architecture as from smaller transistors — design–technology co-optimisation.

28.1Anatomy of a standard cell

Logic is built from standard cells of a fixed height, placed in rows. Height is counted in tracks of minimum metal pitch (for example 6 or 5 tracks); width is counted in contacted poly pitch (CPP), the spacing of transistor gates. A NAND2 might be three or four CPPs wide.

28.2Scaling boosters

Beyond pitch scaling, foundries add scaling boosters: fewer fins or sheets per device, contacts placed over active gates, single diffusion breaks between cells, buried or backside power rails that free routing tracks, and eventually CFET stacking.

28.3Design–technology co-optimisation

DTCO evaluates process choices by their effect on real cells and blocks (area, speed, power, routability) rather than on single transistors. A process feature that looks good alone can fail if cells cannot be routed. imec's 2026 roadmap argues that cell-level gains now matter as much as transistor scaling.

28.4System–technology co-optimisation

STCO extends the idea to the whole system: which functions go on which die, which node each uses, how dies are stacked and connected, and how power and heat are handled — the chiplet and packaging decisions of Modules 9 and 14–15 made together with process choices.

Interconnect and the metal stack

Above the transistors sit fifteen or more layers of copper wiring. At advanced nodes those wires, not the transistors, often decide speed, power and reliability.

29.1The metal stack

The front end of line builds transistors; the back end of line builds the wiring above them. A leading-edge chip has roughly 15–20 metal layers. The lowest layers (M0–M2) have the tightest pitch, in the low twenties of nanometres at 2 nm-class nodes, and connect cells locally. Intermediate layers route between blocks, and a few thick top layers carry the clock, global signals and power with low resistance.

Each layer is made by dual damascene: etch trenches and via holes into a low-k dielectric, line them with a thin barrier (TaN/Ta) and liner, fill them with copper by electroplating, then polish flat with CMP. Low-k dielectrics (k ≈ 2.5–3, versus 3.9 for SiO₂) reduce capacitance but are mechanically weak, which complicates packaging stress.

29.2Resistance, capacitance and delay

Both R and C grow with length L, so the delay of an unbuffered wire grows with L². Shrinking the width makes it worse: the cross-section falls quadratically, and copper's effective resistivity rises above its bulk value of 1.7 µΩ·cm because electrons scatter off surfaces and grain boundaries, while the barrier takes a larger share of the trench. Designers break long wires into segments with repeaters (buffers), which makes delay grow roughly linearly with length at the cost of area and power.

29.3Electromigration and via reliability

At high current density, flowing electrons push metal atoms along the wire. Over years this electromigration opens voids that raise resistance or break the line, and builds hillocks that can short to neighbours. Lifetime follows Black's equation, falling steeply with current density and temperature, so sign-off tools check every power and signal wire against current-density limits. Vias are weak points too: a single via failing can disconnect a net, so tools insert redundant vias where space allows.

29.4New metals and structures

• Ruthenium and molybdenum have shorter electron mean free paths than copper, so they lose less conductivity in very narrow lines and can be used without a barrier.
• Subtractive etch patterns a metal film directly, instead of filling trenches, allowing taller lines and airgaps between them to cut capacitance.
• Backside power delivery (Module 14) moves power wiring under the transistors, freeing front-side tracks for signals and reducing IR drop.
• Hybrid bonding (Module 9) adds wiring between stacked dies, extending the "metal stack" into the third dimension.

Clocking and PLLs

Every synchronous chip runs on a clock. Generating it cleanly and delivering it to billions of flip-flops at the same moment is a design discipline of its own.

30.1Delivering the clock

The clock network drives every flip-flop on every cycle, so it switches more capacitance than any other net; it commonly accounts for a quarter to a third or more of a chip's dynamic power. Clock tree synthesis builds balanced buffer trees (H-trees) so the clock arrives everywhere at nearly the same time. High-performance CPUs add a clock mesh, a grid that shorts the tree's leaves together to average out variation, at the cost of more power.

Skew is the difference in clock arrival between two flip-flops; insertion delay is the time from the clock source to the leaves. Skew can be used deliberately ("useful skew") to borrow time from a short path for a long one.

30.2The cycle-time budget

Every picosecond of skew and jitter is taken from the logic. At 4 GHz the whole cycle is 250 ps, so 25 ps of clock uncertainty costs a tenth of the cycle.

30.3Phase-locked loops

Chips receive a slow, stable reference (often a 25–100 MHz crystal) and multiply it on chip with a phase-locked loop. A phase-frequency detector compares the reference with a divided-down copy of the output; a charge pump and loop filter turn the error into a control voltage; a voltage-controlled oscillator (VCO) changes frequency until the divided output matches the reference in phase.

Ring oscillators are small and widely tunable but noisier; LC oscillators using on-chip inductors have much lower jitter and are used for SerDes (Module 13) and RF (Module 26). Jitter is described as random (Gaussian, from device noise) or deterministic (from supply noise and crosstalk), and specified as period, cycle-to-cycle or long-term jitter. Delay-locked loops align clock phase without generating a new frequency, for example in DRAM interfaces.

30.4Spread-spectrum and adaptive clocking

Spread-spectrum clocking slowly modulates the frequency (for example 0.5% down-spread) so electromagnetic emissions are spread over a band instead of a sharp peak, helping products pass EMI limits. Adaptive clocking detects supply droops when a large block switches on and briefly stretches the clock period, so the chip does not need a voltage margin for the worst droop all the time. Many processors now also run each core or cluster on its own clock and voltage (DVFS, Module 31).

Low-power design

Phones, laptops and data centres are all limited by power. Low-power design cuts it at every level, from cell choice to how software schedules work.

31.1Where the power goes

Dynamic power depends on the activity factor α, switched capacitance C, the square of supply voltage V, and frequency f. Clock gating stops the clock to registers that will not change, cutting α; it is inserted automatically by synthesis and is the single most common power technique. Operand isolation stops inputs to idle arithmetic units from toggling.

31.2Voltage and frequency scaling

Because dynamic energy per operation scales with V², lowering voltage is the strongest lever. But transistors slow down as V approaches the threshold voltage, and leakage keeps flowing for longer per operation. The result is a minimum-energy point, usually a little above threshold. DVFS lets a power-management controller move along this curve: high voltage and frequency for bursts, low for background work.

31.3Leakage control and power domains

• Multi-Vt libraries: fast low-Vt cells only on critical paths, slow high-Vt cells (far less leakage) elsewhere.
• Power gating: header or footer switches cut supply to idle blocks. Retention flip-flops keep state; isolation cells hold the outputs of a powered-off block at safe values.
• Multiple voltage domains: blocks run at different voltages, with level shifters between them.
• Body bias: on FD-SOI processes, adjusting the back-gate voltage trades speed for leakage after manufacture.

This "power intent" is described in the Unified Power Format (UPF, IEEE 1801), which synthesis, place-and-route and verification tools all read, so power-up sequences and isolation are checked as rigorously as logic.

31.4System-level power

At the system level, race-to-idle (finish fast, then power-gate) and pace-to-idle (run slowly at low voltage) compete depending on how much leakage remains when idle. Heterogeneous cores (big.LITTLE, Module 17 and the Phones page) put light tasks on efficient cores. Data-centre accelerators manage power at rack scale, capping chips so a whole row stays within its power budget (Module 14).

Silicon photonics and co-packaged optics

As data rates climb, copper wires reach only a metre or two. Light carries data farther for less energy, and is moving from pluggable modules into the chip package itself.

32.1Why light

Copper loss rises with frequency, so each doubling of lane speed shortens how far a passive cable can reach; at 200 Gb/s per lane passive copper reaches only around a metre or two inside a rack. Beyond that, signals need retimers or optics. Optical fibre loses almost nothing over data-centre distances and can carry many wavelengths on one fibre.

32.2Building blocks

32.3Pluggable, linear and co-packaged

Pluggable transceivers sit at the front panel; the switch chip drives electrical signals across the board to them, and a DSP in the module cleans up the signal. Linear-drive pluggable optics (LPO) remove the DSP and rely on the switch's SerDes, saving power. Co-packaged optics (CPO) put the optical engines in the same package as the switch or GPU, shortening the electrical path to millimetres. NVIDIA (Quantum-X and Spectrum-X Photonics), Broadcom and TSMC (COUPE) are bringing CPO switches into production in 2025–2026.

32.4The hard parts

• Lasers are the least reliable part; external laser sources keep them replaceable.
• Serviceability: a failed pluggable is swapped in seconds; a failed co-packaged engine may mean replacing the whole switch.
• Heat: micro-rings drift with temperature and must be tuned with heaters next to a hot ASIC.
• Test and yield: optical engines must be known-good before they are packaged with an expensive die.

Automotive chips and functional safety

A car chip must work for fifteen years from −40 °C to engine-bay heat, and when it fails it must fail safely. That changes how chips are designed, verified and tested.

33.1Qualification

AEC-Q100 defines stress tests for automotive ICs. Temperature grades include Grade 0 (−40 to +150 °C), Grade 1 (−40 to +125 °C) and Grade 2 (−40 to +105 °C). Lifetimes of 15 years or more and defect rates in the low parts per million, aiming for zero, push suppliers toward mature, well-characterised processes, extra burn-in and screening, and outlier detection in test data.

33.2ISO 26262 and ASILs

ISO 26262 is the functional-safety standard for road vehicles. A hazard analysis rates each failure by severity, exposure and controllability to assign an Automotive Safety Integrity Level from A (lowest) to D (highest); non-safety functions are QM. For hardware, three metrics matter:

One FIT is one failure per billion device-hours. ISO 26262 targets are recommendations for the whole item, which teams allocate down to each chip.

33.3Safety mechanisms

• ECC on memories and buses corrects single-bit and detects double-bit errors.
• Dual-core lockstep: two cores run the same code a few cycles apart, and a comparator flags any difference.
• Logic and memory BIST run at start-up and periodically to find latent faults.
• Watchdogs, voltage and clock monitors detect hangs, droops and clock loss.
• A safety island, a small independent ASIL-D controller, supervises a large ASIL-B compute die and can put the vehicle into a safe state.

Related standards cover what ISO 26262 does not: ISO 21448 (SOTIF) for hazards from functional insufficiency, such as a perception system misjudging a scene, and ISO/SAE 21434 for cybersecurity.

33.4Central compute

Cars are moving from a hundred small controllers to zonal architectures: a few zone controllers near sensors and actuators, connected by automotive Ethernet to one or two central computers. Those computers, such as NVIDIA DRIVE Thor, Qualcomm Snapdragon Ride and in-house designs, are large AI SoCs on leading-edge nodes that must still meet automotive grades, combining the techniques of Modules 10, 16 and 18 with this module's safety discipline.

Capstone: from spec to tape-out

Putting the course together: how a real chip project is scoped, staffed, scheduled, paid for and signed off.

34.1From idea to specification

A specification fixes performance, power and area (PPA) targets, interfaces, the target process and package, and the software that must run on it. Early estimates use the tools of this course: roofline analysis for accelerators (Module 10), cell area and density for die size (Module 28), yield and cost per die (the Cost page), and package and thermal limits (Modules 9 and 15). Make-or-buy decisions for IP, such as CPU cores, SerDes, memory controllers and PHYs, are made here; most chips license more IP than they design.

34.2Team and schedule

Large SoCs take two to three years with hundreds of engineers; verification typically needs more engineers than design. Smaller chips on mature nodes can be done by a few dozen people in a year.

34.3ASIC or FPGA?

An ASIC has a large one-off cost (NRE: design, EDA tools, IP licences, masks) and a low unit cost. An FPGA has almost no NRE but costs far more per unit and uses more power. The break-even volume is where their total costs meet.

34.4Tape-out sign-off checklist

First silicon rarely works perfectly. Teams plan bring-up before tape-out: debug access, spare cells that allow metal-only fixes, and a ranked list of what to test first. A metal-only respin changes a few upper masks and costs far less than a full respin.