SEMICONDUCTOR DESIGN
07 · Flagship chips

The most advanced chips shipping or announced

Public specifications as of November 2026. Vendor figures use different precisions and sparsity conventions, so compare like with like. Items marked reported come from secondary sources, not the vendor.

NVIDIA · 2026

Rubin GPU

Process
TSMC 3 nm-class, CoWoS-L
Dies
2 reticle-size compute + I/O
Transistors
336 B reported
Memory
288 GB HBM4
Bandwidth
up to 22 TB/s
NVFP4
50 PF inference · 35 PF training
NVLink 6
3.6 TB/s per GPU

72 GPUs and 36 Vera CPUs (88 Olympus cores each) form a Vera Rubin NVL72 rack: 3.6 EF NVFP4. In full production, shipping 2H 2026.

NVIDIA · 2025

Blackwell Ultra (B300)

Process
TSMC 4NP, CoWoS-L
Dies
2 compute dies
Transistors
208 B
Memory
288 GB HBM3E
Bandwidth
8 TB/s
FP4
15 PF dense
Power
~1.4 kW

The current volume workhorse in GB300 NVL72 racks. 1.5× the FP4 throughput of B200.

NVIDIA · 2027

Rubin Ultra

Dies
4 reticle-size compute dies
Memory
~1 TB HBM4E
NVFP4
~100 PF
Rack
Kyber, NVL576

Announced roadmap item; figures are targets. Followed by the Feynman generation.

AMD · 2026

Instinct MI455X

Process
TSMC N2 compute + N3 base dies
Architecture
CDNA 5, 8 compute dies
Transistors
320 B reported
Memory
432 GB HBM4, 12 stacks
Bandwidth
~19.6–23.3 TB/s
FP4
~40 PF

The first AMD GPU on TSMC 2 nm. 72 per Helios rack, with 50% more memory than a Rubin rack.

Google · 2025

TPU v7 Ironwood

Design
Dual-die, inference-first
Memory
192 GB HBM3E
FP8
4,614 TFLOPS
Bandwidth
7.37 TB/s, 8 × HBM3E
Scale
9,216 chips per pod

Google's seventh-generation TPU. Google says AlphaChip-generated floorplans have been used in recent TPU generations.

Intel · 2026

Core Ultra 3 · Panther Lake

Process
Intel 18A compute tile
Transistor
RibbonFET (GAA)
Power
PowerVia backside
Launch
CES 2026

The first commercial chip with backside power delivery. Built at Fab 52 in Arizona; 18A yields still improving through 2026.

Memory capacity per accelerator

GB of HBM on package

Memory bandwidth per accelerator

TB/s, vendor peak figures

Apple's A19 and M5 generation is on TSMC N3P; reports say the next generation (A20, M6) moves to base N2. Rubin bandwidth is 22 TB/s in NVIDIA's developer blog and 19.2 TB/s in one NVIDIA spec table; MI455X bandwidth varies between reports.

DEEP DIVEFour NVIDIA generations side by side

The data-centre GPU has changed more in four years than in the previous decade. Each generation added a lower-precision number format, more memory and a faster scale-up link.

H100 (2022)B200 (2024)B300 (2025)Rubin (2026)
ProcessTSMC 4NTSMC 4NPTSMC 4NPTSMC 3 nm-class
Dies12 + NV-HBI22 compute + I/O
Transistors80 B208 B208 B336 B (reported)
Memory80 GB HBM3192 GB HBM3E288 GB HBM3E288 GB HBM4
Bandwidth3.35 TB/s8 TB/s8 TB/sup to 22 TB/s
New formatFP8FP4FP4 (more throughput)NVFP4
Scale-upNVLink 4, 900 GB/sNVLink 5, 1.8 TB/sNVLink 5NVLink 6, 3.6 TB/s

Memory bandwidth grew about 6.5× from H100 to Rubin and capacity about 3.6×, while low-precision compute grew far more — evidence that the industry is fighting the memory wall with HBM4 and wider packages, not only with more FLOPS.

ANATOMYWhat is inside an AI accelerator die

  • Matrix engines (tensor cores, systolic arrays): the bulk of the arithmetic, in FP16/BF16/FP8/FP4.
  • Vector and scalar units for activations, normalisation and control.
  • On-chip SRAM: register files, shared memory and a large L2 cache (tens of MB) to reuse data.
  • Memory controllers and PHYs for HBM along the die edges.
  • Scale-up and scale-out I/O: NVLink or equivalent SerDes, PCIe for the host.
  • Engines for data movement: DMA and tensor-memory accelerators that copy tiles asynchronously.
  • Security and management: root of trust, confidential-computing encryption, telemetry.

TRAINING VS INFERENCETwo different jobs

TrainingHuge matrix multiplies at high arithmetic intensity, backward passes, gradient all-reduce across thousands of chips; limited by compute and interconnect.
Inference prefillProcessing the prompt is compute-bound, similar to training's forward pass.
Inference decodeGenerating one token at a time is memory-bandwidth-bound: every step reads all weights and the KV cache. HBM bandwidth and batching decide throughput.
ConsequenceSome products separate the phases: NVIDIA's Rubin CPX targets prefill with cheaper GDDR7 memory, while HBM parts serve decode.

CUSTOM SILICONHyperscaler accelerators

Cloud companies design their own chips to cut cost and dependence on one supplier: Google's TPUs (now Ironwood, v7), Amazon's Trainium and Inferentia (Trainium2 generally available since late 2024, Trainium3 on a 3 nm-class process), Meta's MTIA and Microsoft's Maia. They are typically designed with partners such as Broadcom, Marvell or Alchip, and built on TSMC processes with CoWoS and HBM — the same supply chain as merchant GPUs.

READING SPECSHow to compare accelerator numbers

  1. Check the number format: FP4 figures are 2× FP8, which is 2× FP16.
  2. Check dense versus sparse: sparse figures assume 2:4 structured sparsity and are double the dense ones.
  3. Divide compute by memory bandwidth to find the ridge point; workloads below it will not reach peak (see the GPU optimization page).
  4. Compare at system level for large models: a 72-GPU rack with a fast scale-up network behaves very differently from eight GPUs in a server.
  5. Look for measured results (MLPerf, independent benchmarks) rather than peak numbers.