Open hardware · Designing a chip without a licence fee

14 · Open hardware

Designing a chip without a licence fee

An open instruction set, open-source EDA and open process design kits now let students and start-ups go from RTL to real silicon for a few hundred dollars.

Instruction set

RISC-V and the RVA23 profile

RVA23, ratified in 2024, fixes a common feature set (including vectors) for 64-bit application processors so one Linux build runs on every compliant chip. Ubuntu requires RVA23 from 25.10; Linux kernel support is landing. Hardware is the lag: by mid-2026 reports still disagreed on whether RVA23 boards were broadly available.

EDA

OpenROAD and LibreLane

OpenROAD performs synthesis-to-GDS physical design (placement, clock tree, routing, timing) with no commercial licence. Paired with the LibreLane flow (formerly OpenLane) it supports open PDKs such as SKY130, GF180MCU and IHP SG13G2, and research PDKs like ASAP7.

Fabrication

Tiny Tapeout and shared shuttles

Tiny Tapeout puts hundreds of small designs on one die and ships each participant a board. After Efabless shut down, shuttles moved to IHP's 130 nm open PDK in Germany; IHP also runs a free multi-project-wafer programme using OpenROAD.

Why it matters

A training pipeline for the industry

Open flows will not tape out a 2 nm GPU, but they teach the whole flow on real silicon, give researchers reproducible baselines (many AI-for-EDA papers use OpenROAD) and lower the cost of first chips for start-ups.

DEEP DIVEThe open flow, step by step

An open-source tape-out follows the same stages as a commercial flow (see design flow), with free tools at every step:

Stage	Open tools	What happens
RTL and simulation	Verilog / SystemVerilog, Chisel, Amaranth; Verilator, Icarus, cocotb	Write the design and test it with simulations and Python testbenches.
Formal checks	SymbiYosys, Yosys-SMTBMC	Prove properties (no deadlock, protocol rules) for all inputs, not just tested ones.
Synthesis	Yosys, ABC	Map RTL to the standard cells of the open PDK.
Floorplan, placement, clock tree, routing	OpenROAD (RePlAce, TritonCTS, TritonRoute)	Place cells, build the clock network and route the wires.
Timing	OpenSTA	Static timing analysis across corners.
Parasitics, DRC, LVS	OpenRCX, Magic, KLayout, Netgen	Extract wire resistance and capacitance, check layout rules, compare layout with the netlist.
Analog and mixed-signal	Xschem, ngspice, Xyce	Schematic capture and transistor-level simulation.
Flow automation	LibreLane (formerly OpenLane), OpenROAD-flow-scripts	Run the whole chain from RTL to GDS with one configuration.

PROCESSESOpen PDKs you can actually fabricate in

SKY130SkyWater 130 nm, the first open PDK (2020, with Google). Mixed-signal, five metal layers.

GF180MCUGlobalFoundries 180 nm, suited to microcontrollers, power and high-voltage designs.

IHP SG13G2IHP 130 nm SiGe BiCMOS from Germany, with fast bipolar transistors for RF; now the main open shuttle target in Europe.

LimitsAll are mature nodes. Leading-edge PDKs remain under NDA, so open flows teach and prototype rather than compete with N3 or N2.

CORESOpen processors worth knowing

Rocket and BOOM (UC Berkeley): in-order and out-of-order RISC-V cores in Chisel, generated through the Chipyard SoC framework.
CVA6 (OpenHW Group): a 64-bit, Linux-capable application core with an industrial verification effort.
XiangShan (Chinese Academy of Sciences): a high-performance out-of-order core taped out in several generations, among the fastest open designs.
OpenTitan: an open silicon root of trust with full documentation and verification, now shipping in commercial products.
Ibex, PicoRV32, SERV: small cores for microcontrollers and teaching; SERV is a bit-serial core of only a few hundred cells.

ECOSYSTEMWhat changed in 2025–2026

Efabless, which ran the Google-sponsored open MPW shuttles and the chipIgnite programme, shut down in 2025. Tiny Tapeout moved its shuttles to IHP and other partners, and the community forked OpenLane as LibreLane. RISC-V's RVA23 profile gave software vendors a stable target, so Linux distributions can ship one image for compliant chips. Commercial RISC-V now ranges from microcontrollers to server and AI-accelerator control cores, while the ISA itself stays royalty-free.

GET STARTEDA realistic first project

Write a small design (a counter, a UART, a tiny CPU) in Verilog and simulate it with Verilator and cocotb.
Run it through LibreLane on SKY130 or IHP SG13G2 and look at the layout in KLayout.
Fix timing and DRC errors until the flow is clean.
Submit it to a Tiny Tapeout shuttle and receive a board with your design on real silicon a few months later.