From sand to a working chip, step by step
A leading-edge chip passes through more than a thousand process steps in a dozen countries before it ships. Pick a stage to see what happens there, the machines and companies involved, the numbers that matter and what can go wrong.
How long does a chip take to make?
Fab cycle time is roughly proportional to the number of mask layers; the industry rule of thumb is one to one and a half days per layer at the leading edge, because each layer needs its own lithography, etch, deposition, clean and measurement steps, and wafers queue at busy tools.
About 25–40 layers suits a mature-node microcontroller; 70–100 a 3 nm or 2 nm processor.
DEEP DIVEThe seven kinds of process step
The thousand-plus steps of a modern flow are combinations of a few basic operations:
| Operation | What it does | Main techniques |
|---|---|---|
| Deposition | Adds a thin film of insulator, metal or semiconductor | Chemical vapour deposition (CVD), atomic layer deposition (ALD, one atomic layer at a time), physical vapour deposition (sputtering), epitaxy, electroplating |
| Lithography | Prints the pattern for one layer in photoresist | EUV (13.5 nm) for critical layers, 193 nm immersion DUV for others, plus coat, bake and develop tracks |
| Etch | Removes material where the resist is open | Plasma (reactive-ion) etch for straight, deep features; atomic layer etch for precision; wet etch for selective removal |
| Doping | Changes conductivity by adding atoms | Ion implantation, then rapid or laser anneal to activate the dopants and repair the crystal |
| Planarisation | Polishes the wafer flat so the next layer can be printed | Chemical-mechanical polishing (CMP) with slurry and pads |
| Cleaning | Removes particles, residues and metals | Wet cleans in ultrapure water and chemicals, megasonic cleaning; roughly a fifth of all steps |
| Metrology and inspection | Measures thickness, line width, overlay and defects | Optical scatterometry, electron-beam review, X-ray; results feed process control |
THE CLEANROOMWhy fabs are the cleanest places on Earth
A single 50 nm particle on a critical layer can short two wires. Cleanroom air is filtered and replaced hundreds of times an hour, flowing down from ceiling filters through a perforated floor. The most critical areas are ISO class 1–3: a cubic metre of air may contain only a handful of particles larger than 0.1 µm, versus millions in ordinary outdoor air. Today the wafers themselves stay sealed in FOUP pods inside mini-environments, so the cleanest air surrounds the wafers rather than the whole room, and people in full suits mainly tend the machines.
THE ARITHMETICWhy every step must be nearly perfect
If each of 1,000 steps ruined one wafer in a thousand, only 37% of wafers would survive. Real fabs reach line yields well above 90%, which means individual steps almost never scrap a wafer. Die yield is a separate question: random defects and systematic patterning problems on each die (see the yield models on the Yield & cost page). Fabs learn yield by tracing failing dies back through wafer maps, inline measurements and electrical test structures to the step and tool that caused them.
GEOGRAPHYWhere each stage happens
| Stage | Main locations | Notes |
|---|---|---|
| High-purity quartz | United States (Spruce Pine), Norway | Crucibles for crystal growth |
| Polysilicon (semiconductor grade) | Germany, US, Japan, Korea | China dominates solar-grade polysilicon |
| Silicon wafers | Japan, Taiwan, Germany, Korea | Five suppliers hold most of the market |
| Equipment | US, Netherlands, Japan | ASML, Applied Materials, Lam, TEL, KLA |
| Leading-edge logic fabs | Taiwan, with new capacity in Arizona, Japan and Germany | Samsung (Korea) and Intel (US, Ireland) also at the leading edge |
| Memory fabs | Korea, US, Japan, China, Taiwan | SK hynix, Samsung, Micron, Kioxia, YMTC, CXMT |
| Assembly and test | Taiwan, China, Malaysia, Vietnam, Korea, Philippines | Advanced packaging for AI chips mostly in Taiwan |
A single chip can cross borders many times: quartz from the US, wafers from Japan, a fab in Taiwan using Dutch and American tools, packaging in Taiwan or Malaysia, and assembly into a server in Mexico or Taiwan. See Geopolitics & supply and Global manufacturing.
LEARN MOREGo deeper on each stage
- Transistor structures and nodes: Process technology · Course Modules 2 and 8
- Printing patterns: Lithography · Course Module 21
- Measuring and yield learning: Course Module 22
- Wiring: Course Module 29
- Packaging and HBM: Packaging & HBM · Chiplets · Course Module 9
- From design to masks: Design flow · Course Module 34