What the newest papers say
A selection of peer-reviewed results and preprints from 2024–2026 that point to how chips will be built and designed next. Preprints on arXiv have not been peer reviewed.
A 32-bit RISC-V processor made of 2D semiconductors
A Fudan University team built a processor that runs standard 32-bit RISC-V instructions on 5,900 MoS₂ transistors, with a full standard-cell library for the 2D process. Atom-thin channels keep gate control at lengths where silicon leaks.
Nature 640, 654–661 →2D CMOS processors with thousands of transistors
Two groups integrated complementary 2D logic, pairing n-type MoS₂ and p-type WSe₂ transistors on single chips. A 2026 Nature Communications paper adds wafer-scale, CMOS-compatible MoS₂ transistors with sub-5 nm channels.
Nature News & Views →Photonic processors run real AI models
"Universal photonic artificial intelligence acceleration" reports a silicon-photonics processor (a 128 × 128 photonic core) that runs ResNet, BERT and an Atari reinforcement-learning agent with near-electronic accuracy.
doi:10.1038/s41586-025-08854-x →AlphaChip and the floorplanning debate
Google's reinforcement-learning macro placer, published in 2021 and renamed AlphaChip in a 2024 addendum, has been used on TPU layouts. Critics questioned reproducibility and the use of commercial-tool initial placements; Google's rebuttal is "That Chip Has Sailed".
arXiv:2411.10053 →LLM agents that write and verify RTL
Benchmarks have moved from single Verilog modules to repository-level tasks. CVDP collects verification and design problems; HORIZON reports completing ChipBench, RTLLM, VerilogEval and nine CVDP categories hands-free, while stressing these are proxies, not solved hardware design.
arXiv:2606.28279 → CVDP →Agents for physical design
PDAGENT-BENCH defines 353 tasks across five capability axes for LLM and vision-language agents driving EDA tools in closed loop through placement, routing and timing closure.
arXiv:2606.17253 →Agentic EDA leaves the lab, slowly
Synopsys announced AgentEngineer on 28 September 2026, citing 50+ customer engagements and general availability at the end of 2026; Samsung and TSMC are the only named users. Cadence offers Maestro models (early access Q4 2026) and the AuraStack super-agent. No independent production metrics, such as tape-outs or time saved, are public yet.
Industry overview →CFET at A7, then 2D
imec places complementary FETs at the A7 node around 2033 and extends its logic roadmap to A3 in 2038, arguing that density gains now come as much from standard-cell height and wiring as from shrinking transistors.
Coverage →HBM4 and co-packaged optics in silicon
Samsung's 12-high, 36 GB HBM4 reaches 3.3 TB/s over 2,048 I/O, and NVIDIA and Broadcom presented co-packaged optical switches, signalling that I/O, not logic, is now the critical design frontier for AI systems.
ISSCC 2026 summary →DEEP DIVEFive research directions and what limits them
1. New transistor structures
After nanosheets, the next steps are forksheet transistors (a dielectric wall between n and p sheets lets them sit closer) and CFET (n and p stacked vertically, roughly halving cell area). The hard parts are making contacts to the lower device, matching n and p performance in one stack, and thermal budget: the upper device must be built without damaging the lower one. Monolithic CFET builds both in one sequence; sequential CFET bonds a second wafer on top.
2. 2D-material channels
Atom-thin MoS₂ and WSe₂ keep gate control at channel lengths where silicon leaks, which is why imec places them in the late 2030s. The open problems are growing defect-free films on 300 mm wafers at temperatures compatible with the rest of the chip, low-resistance metal contacts, a good p-type material, and gate dielectrics that do not trap charge. Processors with thousands of 2D transistors (2025) show the circuits work; matching silicon yield and speed is still far away.
3. Wiring and power delivery
Copper wires get more resistive as they shrink, because electrons scatter off surfaces and grain boundaries, and the barrier layer takes a larger share of the cross-section. Research explores ruthenium and molybdenum lines with no barrier, subtractive etch of metal instead of damascene, airgaps to cut capacitance, and backside power networks that also carry signals. At advanced nodes wire delay and IR drop, not transistor speed, often decide performance.
4. Memory and compute closer together
- 3D DRAM stacks cells horizontally, like NAND, to keep scaling capacity.
- Processing in memory puts simple compute inside DRAM or HBM base dies to avoid moving data.
- Analog in-memory compute uses resistive, phase-change or flash cells to multiply matrices with currents; accuracy, drift and ADC cost limit it.
- Hybrid-bonded SRAM stacked on logic (as in AMD's 3D V-Cache) adds cache without enlarging the compute die.
5. Light and new physics for I/O and compute
Co-packaged optics are moving into products to cut the energy of data movement between chips. Photonic compute for matrix operations shows good accuracy in labs, but converting between electrical and optical signals, laser power and limited precision still restrict it to niches. Superconducting and cryogenic logic, spintronics and quantum processors remain research topics with specific uses rather than replacements for CMOS.
AI FOR CHIPSHow machine learning is entering design
READING PAPERSHow to judge a chip research result
- Single device or circuit? A record transistor is not a working chip; look for ring oscillators, SRAM arrays or processors.
- Wafer scale? Results on small flakes rarely survive the move to 300 mm wafers.
- Variation and yield. Look for distributions across many devices, not the best one.
- Fair baseline. Compare with silicon at the same node and operating point, including energy.
- Peer review. arXiv preprints and conference abstracts are early signals; journal papers and independent replication are stronger.