The same 3 nm, three different chips
The 2025–26 flagship phone processors from Apple, Qualcomm and MediaTek are all built on TSMC N3P, so differences come from architecture, not process. The next round moves to 2 nm.
| Chip | Company | Process | CPU | Notes |
|---|---|---|---|---|
| A19 Pro | Apple | TSMC N3P | 6 cores (2P + 4E) | Leads single-core Geekbench in most reported tests (iPhone 17 Pro) |
| Snapdragon 8 Elite Gen 5 | Qualcomm | TSMC N3P | 8 cores, custom Oryon | Leads multi-core in several reported tests |
| Dimensity 9500 | MediaTek | TSMC N3P | 8 cores, all-big Arm design | Close behind on single-core in early tests |
| M5 | Apple | TSMC N3P | Mac / iPad | Same generation as A19 |
| A20 / M6 | Apple | TSMC N2 reported | — | Reports say Apple uses base N2 rather than N2P for cost and capacity reasons |
| Core Ultra 3 (Panther Lake) | Intel | Intel 18A | Hybrid P/E/LP-E | First PC chip with GAA and backside power |
Benchmark results vary by device, cooling and test version (for example AnTuTu v10 vs v11), so treat leaderboards as indicative. Transistor counts for these chips have not all been published.
DEEP DIVEWhat a phone system-on-chip contains
A flagship phone SoC is a complete computer in about 100 mm² of silicon, designed around a power budget of a few watts sustained and short bursts above that.
| Block | Role |
|---|---|
| CPU cluster | A mix of big performance cores and small efficiency cores; the scheduler moves work between them to save battery. |
| GPU | Graphics and general-purpose compute; recent generations add hardware ray tracing and matrix units. |
| NPU | A neural accelerator for on-device AI — camera processing, speech, and increasingly small language models. |
| ISP | The image signal processor turns raw sensor data into photos and video in real time, often fusing several frames. |
| Modem | 5G/4G baseband (sometimes a separate chip); Apple has begun shipping its own modems. |
| Media and display engines | Video encode/decode, display pipelines with variable refresh rate. |
| Security enclave | Keys, biometrics and secure boot isolated from the main CPUs. |
| Memory interface | LPDDR5X, often stacked on the package to save board space and power. |
POWERDesigning for a few watts
A phone has no fan, so sustained performance is limited by how much heat its glass and metal body can shed — roughly 3–6 W. Designers therefore optimise performance per watt above all: wide but slower-clocked cores, many voltage and power domains, aggressive clock and power gating, and dedicated accelerators that do a task at a fraction of the CPU's energy. Peak benchmark scores often reflect short bursts before thermal throttling.
WHY SAME NODE, DIFFERENT RESULTSArchitecture matters
Apple, Qualcomm and MediaTek all used TSMC N3P in their 2025 flagships, yet results differ because of design choices: Apple's very wide cores with large caches favour single-thread speed; Qualcomm's custom Oryon cores and MediaTek's all-big-core Arm designs favour multi-core throughput. Cache sizes, memory latency, GPU design and software tuning decide the rest.
PCSThe laptop chip shift
ON-DEVICE AIWhy NPUs and memory bandwidth matter
Running a language model on a device is limited mostly by memory: every generated token reads the model's weights, so a 3-billion-parameter model at 4-bit precision needs roughly 1.5 GB read per token. LPDDR5X bandwidth (tens to about a hundred GB/s on phones, several hundred GB/s on large laptop chips) therefore sets generation speed more than NPU TOPS. Quantisation, smaller models and speculative decoding — the same techniques described on the GPU optimization page — apply on devices too.