Printing features smaller than a virus
The smallest printable half-pitch follows the Rayleigh criterion, CD = k₁·λ / NA. EUV uses 13.5 nm light; High-NA EUV raises the numerical aperture from 0.33 to 0.55. Intel completed acceptance of ASML's EXE:5200B in late 2025 and is designing 14A around it, while TSMC has so far stayed with 0.33-NA EUV and multi-patterning.
k₁ below ~0.3 needs aggressive resolution-enhancement tricks; the physical limit for a single exposure is 0.25.
The workhorse
Every leading node since 7 nm uses EUV for its tightest layers. Below ~28 nm pitch, single exposures run out of room and fabs use two or more exposures per layer.
Bigger lens, half the field
Anamorphic optics shrink the exposure field to half the standard reticle, so dies larger than ~26 × 16.5 mm must be stitched. imec targets qualification of its EXE:5200 by Q4 2026.
Cost per layer
A High-NA scanner costs several hundred million dollars. Whether one exposure beats two cheaper ones decides when each foundry adopts it; analysts expect TSMC around the end of the decade.
DEEP DIVEInside an EUV scanner
An EUV lithography system is one of the most complex machines ever built — about the size of a bus, shipped in dozens of crates, and made by a single company, ASML.
- Light source. A high-power CO₂ laser hits droplets of molten tin, about 50,000 per second, first flattening each droplet with a pre-pulse and then vaporising it into a plasma that emits 13.5 nm light. Source power of several hundred watts is needed for economic throughput.
- Collector and illuminator. A multilayer mirror collects the light; illuminator mirrors shape it into the required angular pattern (dipole, quadrupole or freeform) that is optimised per layer together with the mask.
- Reticle stage. The reflective mask moves at high speed, synchronised with the wafer stage to nanometre accuracy.
- Projection optics. Six mirrors (more in High-NA systems) demagnify the pattern four times. Each mirror reflects only about 70% of EUV light, so only a few percent of the source power reaches the wafer.
- Wafer stage. Two wafer stages work in parallel — one measured, one exposed — moving with accelerations of several g while keeping overlay errors to a nanometre or two.
- Vacuum. The whole beam path is in vacuum, because air absorbs EUV, with a thin hydrogen atmosphere to keep tin debris off the optics.
PATTERNINGPrinting below the limit: multiple patterning
When a pitch is smaller than one exposure can resolve, fabs split or multiply patterns:
- LELE (litho-etch-litho-etch): two exposures, each printing every other line. Cheap in steps but sensitive to overlay between the two.
- SADP / SAQP (self-aligned double / quadruple patterning): one printed line is coated with a spacer film; etching leaves spacers on both sides that become two (or four) lines at half (or a quarter) the pitch. Overlay-free but limited to regular line arrays, which is why advanced layouts use strict one-directional "gridded" designs cut by separate block masks.
- EUV single exposure replaced several DUV quadruple-patterning steps at 7–5 nm; at 2 nm and below some EUV layers need double patterning again, which High-NA aims to avoid.
HIGH-NAWhat changes with 0.55 numerical aperture
Higher NA resolves smaller features (down to roughly 8 nm half-pitch) and improves image contrast, but costs depth of focus, which scales as λ/NA². To fit the larger angles, the optics are anamorphic: they demagnify 8× in one direction and 4× in the other, halving the exposure field. Dies larger than half a field must be stitched from two exposures, which affects the layout of very large chips such as AI accelerators. Resists must also be thinner because of the shallower focus.
RESISTThe chemistry that records the image
Chemically amplified resists use one photon to release an acid that catalyses many reactions during a post-exposure bake — sensitive, but the acid diffuses and blurs edges. Metal-oxide resists (tin-oxide clusters) absorb EUV more strongly and resolve finer lines, and dry-deposited resists are being introduced. Resist sensitivity, resolution and line-edge roughness cannot all be improved at once (the "RLS trade-off"), which is the practical limit behind stochastic defects.
COSTWhy lithography decides wafer cost
Lithography is the single largest equipment cost in a leading-edge fab. Each EUV exposure consumes scanner time, so the number of EUV layers, the dose per layer and the number of multiple-patterning steps feed directly into wafer price. Leading-edge processes use on the order of twenty or more EUV exposures plus dozens of DUV exposures. Choosing between High-NA single exposure and 0.33-NA double patterning for each layer is therefore an economic calculation as much as a technical one. See the course module on computational lithography for OPC, masks and photon shot noise.