Standard plugs between dies
Once a product is split into chiplets, the link between them decides how much the split costs in power and latency. UCIe is the open die-to-die standard; NVIDIA's NVLink Fusion lets other companies' CPUs and accelerators join an NVLink fabric through a UCIe bridge.
UCIe 1.x/2.0 top out at 32 GT/s; UCIe 3.0 (Aug 2025) adds 48 and 64 GT/s, backward compatible. Target bit-error rate: 10⁻¹⁵ at 48 GT/s, 10⁻¹² at 64 GT/s.
UCIe 3.0
Doubles UCIe 2.0's 32 GT/s with 48 and 64 GT/s modes for both organic (UCIe-S) and silicon-bridge (UCIe-A) packages, adds runtime recalibration for power-efficient link tuning and a longer sideband for multi-chip layouts.
NVLink Fusion
Opens the NVLink scale-up fabric to third-party silicon. Custom CPUs and XPUs connect through a UCIe-to-NVLink bridge chiplet supplied by NVIDIA; Qualcomm and Fujitsu CPUs and Ayar Labs optical I/O have been announced partners.
Edge length is the budget
Die-to-die bandwidth scales with the length of die edge you give to PHYs. Every millimetre used for chiplet links is not available for HBM or SerDes, which is why 3D stacking (SoIC) and faster lanes both matter.
DEEP DIVEHow products are split into chiplets
There is no single chiplet recipe; companies split designs along different lines depending on what limits them.
| Product | How it is split | Why |
|---|---|---|
| AMD EPYC / Ryzen | Up to 16 CPU core dies (CCDs) on the newest node around a central I/O die on an older node | Reuse one small core die across many products; I/O does not benefit from the newest node |
| AMD Instinct MI300X | 8 compute dies (XCDs) hybrid-bonded on top of 4 I/O dies, 8 HBM3 stacks, 153 billion transistors | 3D stacking keeps compute close to cache and memory controllers |
| NVIDIA B200 / Rubin | Two reticle-size compute dies acting as one GPU, joined by a 10 TB/s die-to-die link (NV-HBI on Blackwell) | Exceed the reticle limit while software sees a single device |
| Apple M Ultra | Two Max dies joined by the UltraFusion bridge (about 2.5 TB/s) | Double the chip without designing a new die |
| Intel Ponte Vecchio | 47 active tiles from several processes and foundries using EMIB and Foveros | Mix processes and suppliers per function |
METRICSHow die-to-die links are judged
STANDARDSUCIe, BoW and proprietary links
UCIe (Universal Chiplet Interconnect Express), first released in 2022, defines the physical layer, a die-to-die adapter and protocol mappings for PCIe, CXL and raw streaming. UCIe 2.0 added management and 3D stacking support; UCIe 3.0 (2025) doubled data rates to 64 GT/s. Other open efforts include Bunch of Wires (BoW) from the Open Compute Project. In practice, the highest-performance products still use proprietary links tuned for their packages — NVLink-C2C connects NVIDIA's Grace CPU to its GPU at 900 GB/s, for example — while UCIe enables mixing dies from different vendors.
CHALLENGESWhat makes multi-die design hard
- Partitioning: traffic that crosses a die boundary costs power and latency, so the split must follow the data flow.
- Thermal coupling: a hot compute die heats its neighbours; stacked dies trap heat in the middle.
- Test: each die needs test access before assembly, and the assembled package needs tests that can isolate a failing link.
- Power delivery: stacked dies need power to pass through the bottom die with TSVs.
- Security and trust: mixing dies from different vendors raises questions of authentication and attestation of each die.
- EDA: tools must plan, time and verify across dies, interposer and package together — the "3D-IC" flows the major EDA vendors now sell.
OUTLOOKA chiplet marketplace?
The long-term vision is buying chiplets like IP blocks today: a CPU die from one vendor, an I/O die from another, an accelerator from a third. Standard interfaces exist, but a market needs interoperable physical form factors, test standards, shared liability for failures and packaging capacity open to many customers. For now, most multi-die products still come from one company combining its own dies.