Who actually makes the chips
Almost every leading-edge chip on this page is made by one company. In Q2 2026 TSMC held a record share of the foundry market, while new fabs in the US and Japan try to spread the supply chain beyond Taiwan.
Foundry revenue share, Q2 2026
Top-10 revenue was a record ~$53.5 B (+11.5% QoQ). Counterpoint puts TSMC at 73% and ranks SMIC ahead of Samsung; TrendForce has Samsung 5.9% vs SMIC 5.4%.
Where 2–4 nm wafers are made
- Taiwan — TSMC N2 in volume since Q4 2025 (Hsinchu, Kaohsiung)
- Arizona, US — TSMC Fab 1 on N4 since late 2024 with Taiwan-level yields; Fab 2 tooling reported from Q3 2026 for 3 nm in 2027; Fabs 3–4 planned for N2/A16
- Arizona, US — Intel Fab 52 making 18A (Panther Lake)
- Hokkaido, Japan — Rapidus 2 nm pilot line since April 2025; mass production targeted for 2H 2027
- Korea — Samsung SF2 (2 nm GAA), which also began volume production in Q4 2025
- China — SMIC N+3 (DUV only), see Geopolitics
Rapidus: can a new foundry win customers?
Rapidus has shown working 2 nm GAA transistors, raised ¥267.6 billion in February 2026 (¥100 billion via the state's IPA, the rest from 32 companies) and says it is talking to 60+ potential customers, mainly US hyperscalers and ASIC designers. No high-volume customer has been announced.
One company, ~72% of revenue
TSMC's share is far higher at the leading edge, where it makes nearly all AI accelerators and flagship phone chips. That concentration is the reason behind subsidies such as the US CHIPS Act and Japan's support for Rapidus.
Fabs take years
After tools are installed, qualifying a line and ramping output can take up to a year. Announced dates for overseas fabs have repeatedly moved, in both directions, as demand and subsidies change.
DEEP DIVEInside a leading-edge fab
A modern "gigafab" is a building several hundred metres long built around a cleanroom where air is filtered so that a cubic metre holds only a handful of tiny particles. Wafers travel in sealed pods (FOUPs) carried by overhead robots between hundreds of tools, and humans in full suits rarely touch them.
EQUIPMENTWho makes the tools
| Company | Main tools |
|---|---|
| ASML (Netherlands) | Lithography scanners; sole supplier of EUV |
| Applied Materials (US) | Deposition, etch, implant, CMP, inspection |
| Lam Research (US) | Etch and deposition, especially for memory |
| Tokyo Electron (Japan) | Coater/developer tracks, etch, deposition, cleaning |
| KLA (US) | Inspection and metrology |
| Others | Screen, Hitachi High-Tech, ASM International, Kokusai, Advantest and Teradyne (test), Disco (dicing) |
OPERATIONSRunning the fab
- Automation: automated material handling systems move tens of thousands of wafer pods a day; scheduling software decides which lot goes to which tool next.
- Process control: inline measurements after critical steps, statistical process control and advanced process control that adjusts tool settings lot by lot.
- Yield ramp: new nodes start with low yield; engineering teams find and fix systematic defects until yield reaches maturity. Speed of ramp is a key competitive advantage.
- Workforce: process, equipment, yield and integration engineers and technicians; staffing new fabs abroad has been one of the hardest parts of expansion.
MEMORYMemory fabs are different
DRAM and NAND fabs are run by the memory companies themselves (Samsung, SK hynix, Micron, Kioxia/WD, YMTC, CXMT). DRAM is fighting capacitor and cell scaling with EUV and new architectures such as vertical-channel and 3D DRAM; NAND grows upward, with more than 200 layers in production and higher counts announced. HBM production also needs TSV and stacking lines, which limited supply in 2024–2026.
BACK ENDAssembly and test
After the fab, wafers go to assembly and test — historically outsourced to OSATs such as ASE, Amkor and JCET, mostly in Asia. Advanced packaging for AI chips is now done largely by foundries themselves (TSMC CoWoS and SoIC), and packaging capacity has been as much of a bottleneck as wafer capacity.