01Specification

The specification turns a market need into numbers an engineering team can design against. For an AI accelerator that means target throughput at each number format (FP8, FP4), memory capacity and bandwidth, scale-up bandwidth to neighbouring chips, power envelope per package, the software stack it must run, and the target cost and launch date. For a phone SoC it means battery-life targets, camera and modem features, and a thermal limit of a few watts.

Inputs and outputs

• In: customer and product requirements, competitive analysis, roadmap of available processes, IP and packaging, software requirements.
• Out: a product requirements document and a top-level micro-specification: interfaces (PCIe generation, number of HBM stacks, SerDes lanes), power and area budgets, and a feature list frozen for the first tape-out.

Key decisions

Which process node and packaging technology to use (this fixes cost and schedule more than any other choice), what to build in-house versus license, and which features are deliberately left out. Late feature additions are the most common cause of schedule slips.

Where it goes wrong

Under-specifying power and memory bandwidth, assuming a process or package will be ready on time, and specifications that keep changing after RTL starts.

02Architecture

Architects decide how the specification will be met: how many compute units, how large the caches, how the on-chip network connects them, how memory controllers are arranged and how the design is split into dies (chiplets). Decisions are made with performance models — from spreadsheets and analytical roofline models to cycle-approximate simulators running real workloads.

Inputs and outputs

• In: specification, workload traces (for AI: the layers and batch sizes of target models), process and memory characteristics.
• Out: block diagram, micro-architecture specifications for each block, area and power estimates, a performance model that later stages are checked against.

Methods

Design-space exploration sweeps parameters (array size, cache size, bandwidth) against workloads. Roofline analysis shows which workloads are compute-bound and which are memory-bound, which in turn decides whether silicon area should go to more arithmetic, more SRAM or more memory interfaces. For multi-die products, architects also choose the partition: which functions need the newest node and which can sit on cheaper dies.

Where it goes wrong

Optimising for benchmarks that do not represent real use, and underestimating data movement: on modern chips, moving data often costs more energy than computing on it.

03RTL design

Engineers write the hardware at register-transfer level, mostly in SystemVerilog: registers, the combinational logic between them, finite-state machines and interfaces. Some teams generate RTL from higher-level languages (Chisel, SpinalHDL) or from C++ through high-level synthesis, especially for datapaths and accelerators.

What good RTL looks like

• Synchronous design with clear clock and reset domains; every crossing between clocks goes through a synchroniser or asynchronous FIFO.
• Parameterised, reusable blocks with documented interfaces (AXI, CHI, custom streaming protocols).
• Written with timing in mind: logic depth per pipeline stage matched to the target frequency, and no structures that synthesis tools cannot implement efficiently.
• Lint-clean: static checks for latches, combinational loops, width mismatches and coding errors run on every change.

Integration

A large SoC integrates hundreds of IP blocks — CPU clusters, memory controllers, PCIe and UCIe controllers and PHYs, security engines. Integration RTL, register maps and connectivity are often generated from machine-readable descriptions (IP-XACT, SystemRDL) to avoid manual errors.

Where AI is entering

LLM-based assistants and agents now draft RTL, testbenches and assertions; benchmarks such as VerilogEval, RTLLM and CVDP measure them, and EDA vendors are shipping agentic tools. On production IP their output is still reviewed and verified like human code.

04Verification

Verification proves that the RTL does what the specification says before money is spent on masks. On complex chips it consumes more engineering effort than design itself, and a dedicated verification team often outnumbers the designers.

Techniques

• Simulation with UVM testbenches: constrained-random stimulus, scoreboards that compare the design against a reference model, and assertions inside the RTL.
• Coverage closure: code coverage (lines, branches, toggles) and functional coverage (did we exercise every mode, corner case and interaction listed in the verification plan?). Sign-off requires agreed coverage targets.
• Formal verification: mathematically proves properties for all possible inputs — ideal for arbiters, protocol compliance, deadlock freedom and security properties; equivalence checking proves later netlists match the RTL.
• Emulation and FPGA prototyping: hardware boxes (Palladium, ZeBu, Veloce) run the design a million times faster than simulation, so firmware, drivers and real workloads can run months before silicon.

Metrics

Bug discovery rate (it should fall towards zero before tape-out), coverage percentages, regression pass rate and the number of open high-severity issues. Industry surveys report that only a minority of projects achieve working first silicon, with logic and functional bugs the leading cause of respins.

05Logic synthesis

Synthesis maps RTL onto the foundry's standard-cell library: NAND, NOR, flip-flops, multiplexers and hundreds of variants in different sizes and threshold voltages. The tool optimises the netlist for timing, area and power under the constraints written in SDC: clock definitions, input and output delays, false paths and multicycle paths.

What the tool decides

• Logic restructuring (factoring, retiming registers across logic to balance stages).
• Cell selection and sizing: larger cells drive more load faster but use more area and power.
• Threshold-voltage mix: low-V_t cells only where timing needs them, high-V_t elsewhere to limit leakage.
• Clock gating insertion to cut dynamic power.

Checks

Logical equivalence checking proves the netlist matches the RTL. Early timing and power reports show whether the architecture can close at the target frequency; if not, the problem goes back to RTL or architecture rather than being left for physical design.

06Design for test (DFT)

Every manufactured die must be tested in seconds on automatic test equipment, so test structures are designed into the chip.

• Scan insertion: flip-flops are converted to scan cells and linked into chains so the tester can shift in patterns, capture one functional clock and shift out results. Compression logic reduces the data and time needed.
• ATPG: automatic test pattern generation creates patterns for stuck-at, transition (at-speed) and cell-aware fault models; the goal is typically well above 98–99% fault coverage.
• Memory BIST and repair: built-in self-test runs march algorithms on every SRAM; failing rows and columns are replaced by spares and the repair is stored in fuses.
• Boundary scan and monitors: JTAG access, on-die process, voltage and temperature sensors, and for chiplets, test access through die-to-die links so each die can be tested before and after assembly.

DFT costs a few percent of area and must not break timing, so it is planned during architecture, not added at the end.

07Floorplanning, placement and routing

Physical design turns the netlist into geometry on the die.

Floorplan and power plan

Engineers fix the die outline, place hard macros (SRAMs, PHYs, analog blocks) and I/O bumps, define voltage domains and build the power grid. For HBM-based accelerators, the positions of HBM PHYs along the die edge and the interposer routing are fixed early because they constrain everything else.

Placement

Millions to billions of standard cells are placed in rows, first globally then legalised, minimising wire length and congestion while meeting timing. Hierarchical designs place and route large blocks separately, then assemble them at the top level.

Clock-tree synthesis

A buffered tree or mesh distributes each clock to every flip-flop with controlled skew. The clock network can account for a large fraction of dynamic power, so useful skew and clock gating are exploited aggressively.

Routing

Signals are routed on a stack of a dozen or more metal layers, observing thousands of design rules and double- or multi-patterning colouring at the tightest pitches. With backside power delivery (Intel 18A, TSMC A16), power moves to the wafer's back side and front-side tracks are freed for signals.

Optimisation loop

After each step, timing, congestion, IR drop and crosstalk are analysed and the tool resizes, buffers and reroutes. Reinforcement-learning placement (AlphaChip) and ML-driven tool tuning are used to explore these trade-offs faster.

08Sign-off

Before tape-out, the design must pass a set of independent, conservative analyses:

Late engineering change orders (ECOs) fix the last violations with minimal edits; a metal-only ECO, changing only wiring layers, can even be applied after tape-out to save the cost of a full new mask set.

09Tape-out and mask making

The final layout is streamed out as GDSII or OASIS and sent to the foundry — still called "tape-out" from the days of magnetic tape. The foundry runs its own checks, then optical proximity correction and, increasingly, inverse lithography to compute mask shapes that will print correctly. Masks are written by electron-beam or multi-beam writers and inspected for defects. A leading-edge product needs dozens of masks (more than 70 layers at advanced nodes), and a full set costs tens of millions of dollars.

Companies often tape out a smaller test chip first to characterise IP and the process, and some foundries offer multi-project wafers where several customers share one mask set.

10Fabrication

Wafers pass through roughly a thousand process steps over about three months: deposition, lithography, etch, implant, anneal, polish and clean, repeated for every layer. Lots are tracked through the fab with inline measurements; split lots run deliberately varied process conditions to see how the design behaves across the process window. The first wafers out of the fab ("first silicon") go straight to bring-up.

11Packaging, test and bring-up

Wafers are probed and good dies identified (wafer sort). Dies are thinned, diced and assembled: flip-chip onto substrates, or onto CoWoS interposers with HBM stacks, or stacked with hybrid bonding. Packages are tested again (final test, system-level test) and binned by speed and power.

In the lab, bring-up teams power the chip, boot firmware, run diagnostics and workloads, and characterise frequency, power and thermals across voltage and temperature. Bugs found here are fixed in firmware where possible, by metal ECO, or in a new stepping. Qualification then stresses parts for reliability (high-temperature operating life, temperature cycling) before volume production and customer shipments.