Why big dies are expensive, and chiplets help
A random defect kills the die it lands on, so the fraction of good dies falls exponentially with area. Splitting one large die into chiplets raises yield, at the cost of packaging and die-to-die interfaces. Adjust the sliders to see the trade-off on a 300 mm wafer.
Dies per wafer = π(d/2)²/A − πd/√(2A) for wafer diameter d. Murphy's model Y = ((1 − e^(−AD₀)) / AD₀)²; Poisson Y = e^(−AD₀). Chiplet cost here covers silicon only, not packaging, testing or the extra area for die-to-die links. Wafer prices for leading nodes are not published; ~$30k for N2 is a widely reported estimate.
Cost per transistor has stopped falling
Baseline: N3E at $25k per wafer and density 1.00× = index 100. TSMC does not publish prices; figures are supply-chain estimates (TrendForce: N2 +10–20% over N3; earlier rumours said +50%).
Cost per transistor by node
The historic engine of Moore's law was a falling cost per transistor. If a new node raises wafer prices about as fast as it raises density, the cost per transistor stays flat, and the remaining gains come from power, performance and packaging. That is one reason I/O and cache dies stay on older nodes in chiplet designs such as AMD's MI455X.
DEEP DIVEWhere the money goes
The cost of a chip has three layers: the one-off cost to design it, the cost per wafer to make it, and the cost per good unit after yield, packaging and test.
YIELD MODELSThree ways to model defects
Poisson assumes defects land completely at random and is pessimistic for large dies. In reality defects cluster, so some dies collect several while others have none; the negative binomial model captures this with a clustering parameter α (typically 1–5). Foundries quote D₀ for mature processes around 0.05–0.1 defects/cm² and higher during a new node's ramp.
SAVING DIESRedundancy and binning
- Redundancy: spare SRAM rows and columns, and spare compute units, let many defective dies be repaired. GPUs typically ship with some streaming multiprocessors disabled so dies with a defect in one unit can still be sold.
- Binning: dies are sorted by speed, leakage and working units into product tiers. One die design can become several products at different prices.
- Partial good dies make large dies economical — without them, a 800 mm² die at D₀ = 0.1 would yield only around 45–47%.
WORKED EXAMPLEMonolithic versus four chiplets
| Assumption: N2-class wafer at $30k, D₀ = 0.1/cm², Murphy model | One 800 mm² die | Four 200 mm² chiplets |
|---|---|---|
| Gross dies per 300 mm wafer | ~64 | ~306 |
| Die yield | ~47% | ~82% |
| Good dies per wafer | ~30 | ~251 (≈ 62 sets of four) |
| Silicon cost per product | ~$1,000 | ~$480 + packaging and die-to-die overhead |
The chiplet version needs extra area for die-to-die interfaces (often 5–10%), advanced packaging and known-good-die testing, so the real advantage is smaller — but it grows as dies get larger or defect density higher. Use the calculator above to try other values.
TRENDThe end of cheaper transistors
For decades each node made transistors cheaper. With wafer prices now rising about as fast as density, cost per transistor has roughly flattened at the leading edge. The consequences are visible across the industry: only products that need peak performance or efficiency move to the newest node, I/O and analog stay on older nodes, chiplets and packaging absorb more of the innovation, and mature-node capacity remains economically important.