The transistor, rebuilt every few years
The FinFET carried the industry from 22 nm to 3 nm. At 2 nm the gate now wraps the channel on all four sides (gate-all-around nanosheets), power is moving to the back of the wafer, and the roadmap continues with stacked CFETs and 2D-material channels.
Leading-edge logic nodes
| Node | Company | Transistor | Power delivery | Status (Nov 2026) | Claimed gain |
|---|---|---|---|---|---|
| N3P | TSMC | FinFET | Front side | Volume; Apple A19 / M5 generation | Optimised 3 nm |
| N2 | TSMC | GAA nanosheet | Front side | HVM since Q4 2025; ~8% of wafer revenue in Q3 2026 | First TSMC GAA node |
| N2P | TSMC | GAA nanosheet | Front side | 2026 ramp | ~5% over N2 (reported) |
| A16 | TSMC | GAA nanosheet | Super Power Rail (backside) | Development complete; volume Q4 2026 or 2027 (sources differ) | 8–10% faster or 15–20% less power vs N2P |
| N2U | TSMC | GAA nanosheet | Front side | 2028 | 3–4% speed or 8–10% power, 1.02–1.03× density vs N2P |
| A14 | TSMC | 2nd-gen GAA | Front side (backside version = A12, 2029) | 2028 | Up to 15% speed or 30% less power vs N2 |
| A13 | TSMC | 2nd-gen GAA | — | 2029 | 6% area saving vs A14 |
| 18A | Intel | RibbonFET (GAA) | PowerVia (backside) | Shipping in Panther Lake since CES 2026; yields improving | First commercial backside power |
| 14A | Intel | RibbonFET 2 | PowerDirect (backside) | Customer decisions 2H 2026–1H 2027; volume ~2028 | Designed to use High-NA EUV |
| SF2 | Samsung | MBCFET (GAA) | Front side | 2025–26 ramp | Samsung's 3rd-gen GAA |
SRAM scales again. TSMC reports a 0.0175 µm² high-density SRAM bit cell on N2 (≈38 Mb/mm² macros), about 17% smaller than the 0.021 µm² cell that N3E and N5 shared. Independent measurements of N2 logic density are not yet public; TSMC claims ~15% over N3E for mixed designs.
"N2", "18A" and the like are marketing names, not physical gate lengths. Compare nodes by measured density, speed and power on the same design. A 2026 teardown of Panther Lake put Intel 18A close to TSMC N3E in density, with newer TSMC nodes still ahead.
Better gate control
Wrapping the gate around stacked silicon sheets suppresses leakage at short channel lengths and lets designers choose sheet width per cell, trading drive current for power.
Wires on both sides
Moving power rails under the transistors frees front-side metal for signals, cuts IR drop and improves density. Intel shipped it first (PowerVia); TSMC follows with Super Power Rail in A16.
- Intel 4 test chip (VLSI 2023): ~30% less IR droop, 5–6.7% higher frequency, >90% cell utilisation
- Intel 18A (VLSI 2026): peak dynamic droop under 10 mV vs over 90 mV on front-side Intel 3
- Routed Arm sub-block: +9% performance at iso-power, or −18% power at iso-performance
Stack the transistors
imec's 2026 roadmap sees complementary FETs (nMOS on top of pMOS) arriving around the A7 node (~2033), then 2D-material channels, and extends to A3 by 2038.
DEEP DIVEHow a gate-all-around transistor is built
A nanosheet transistor at 2 nm is built in a sequence that looks like a FinFET process with several clever additions. The key idea is to grow a stack of alternating silicon and silicon-germanium layers, shape it into fins, and late in the process dissolve the SiGe so the gate can wrap around each silicon sheet.
- Superlattice epitaxy. Three or four pairs of Si and SiGe layers, each a few nanometres thick, are grown on the wafer with atomic-level control. The silicon layers will become the channels; SiGe is sacrificial.
- Fin patterning. Lithography and etch cut the stack into fins whose width sets the sheet width — the designer's knob for drive current. Shallow-trench isolation fills the space between fins.
- Dummy gate. A polysilicon placeholder gate is patterned across the fins at the contacted poly pitch (roughly 45–50 nm at 3–2 nm class nodes).
- Inner spacers. The SiGe layers are recessed sideways and the gaps filled with a dielectric. These inner spacers isolate the future gate from the source and drain and reduce parasitic capacitance — a step with no FinFET equivalent.
- Source and drain epitaxy. Heavily doped silicon (nMOS, phosphorus) or SiGe (pMOS, boron) is grown at each end of the sheets, also straining the channel to raise carrier mobility.
- Replacement metal gate and channel release. The dummy gate is removed, the SiGe between the silicon sheets is etched away selectively, and the now-suspended sheets are coated all around with a high-k dielectric (hafnium oxide) and work-function metals that set the threshold voltage, then filled with gate metal.
- Contacts and local interconnect. Tungsten, cobalt or ruthenium contacts reach the source, drain and gate; contact resistance is now one of the largest parasitics.
- Back end of line. Fifteen or more metal layers are built above. At the tightest pitches copper's resistance rises sharply because the barrier liner takes up much of the cross-section, so ruthenium, molybdenum and other liner-free metals and air-gap dielectrics are introduced.
- Backside power (A16, 18A). The wafer is bonded face-down to a carrier, thinned from the back to within a few hundred nanometres of the transistors, and power contacts and wires are built on the back side.
PPAWhat each generation actually delivers
Foundries quote improvements as either more speed at the same power, or less power at the same speed, plus density. Typical full-node claims have shrunk over time:
| Transition | Speed at iso-power | Power at iso-speed | Logic density |
|---|---|---|---|
| TSMC N3E → N2 | +10–15% | −25–30% | ~1.15× (mixed design) |
| TSMC N2P → A16 | +8–10% | −15–20% | 1.07–1.10× |
| TSMC N2 → A14 | up to +15% | up to −30% | full-node gain claimed |
| TSMC A14 → A13 | — | — | 6% area saving |
The pattern is clear: density gains per node are now 10–20% rather than the historic 2×, so architecture, chiplets and packaging carry more of the improvement.
NAMINGWhy "2 nm" is not 2 nanometres
Until the late 1990s a node name roughly matched the transistor's gate length. As structures went 3D, names became marketing labels that continue the old scaling sequence. A "2 nm" transistor has a gate pitch of tens of nanometres; the sheets themselves are a few nanometres thick. Intel renamed its nodes in 2021 (Intel 7, 4, 3, 20A, 18A) to align with the foundry convention. Fair comparisons use measured transistor density, SRAM cell area, gate and metal pitch, and speed–power curves on the same design.
SRAMMemory scaling is the hidden bottleneck
SRAM caches occupy a large share of CPU and AI accelerator area. The high-density SRAM bit cell stalled at about 0.021 µm² from N5 to N3E, then shrank to about 0.0175 µm² at N2 thanks to nanosheets. Where SRAM does not scale, designers move cache to separate, cheaper dies stacked on top (AMD's 3D V-Cache) or use more HBM.
VARIATIONMaking billions of identical transistors
Atomic-scale differences make every transistor slightly different: random dopant fluctuations (reduced by undoped channels), line-edge roughness, metal grain structure and sheet-thickness variation. Variation forces designers to add timing margins and higher supply voltages, so process control (see the manufacturing page) translates directly into performance and power.