The package is now part of the chip
A single reticle caps a die at ~830 mm². Today's AI accelerators exceed that by placing several compute dies and up to twelve HBM stacks on a silicon interposer (TSMC CoWoS), or by bonding dies directly on top of each other (SoIC). Memory bandwidth, not raw compute, often sets performance.
Presets: B300 · Rubin · MI455X · Samsung HBM4 max
Chip-on-wafer-on-substrate
- 5.5-reticle interposers in production, with reported yields above 98%
- 14-reticle version (~10 compute dies, 20 HBM stacks) planned for 2028
- 40-reticle system-on-wafer (SoW-X) expected in 2029
- Capacity reported at roughly 130k wafers/month by late 2026 reported
A logic die at the bottom of the stack
- 2,048-bit interface; ~2–3.3 TB/s per stack depending on pin speed
- Base die now made on a logic process: Samsung in-house 4 nm, SK hynix on TSMC 12 nm
- Samsung announced mass production in Feb 2026 at 11.7 Gb/s; SK hynix and Micron ramped during 2026
- 16-high, 48 GB stacks shown at CES 2026
True 3D stacking
Hybrid bonding joins dies copper-to-copper with micron-scale pitch. TSMC's A14-on-A14 SoIC (2029) promises 1.8× the die-to-die I/O density of N2-on-N2.
Light leaves from inside the package
TSMC's COUPE photonic engine moves the optical transceiver next to the switch or GPU. TSMC claims 2× power efficiency and 10× lower latency than pluggable optics, with on-substrate production starting in 2026.
DEEP DIVEFrom bumps to bonds: interconnect density
Packaging progress is measured by how closely connections between die and package, or die and die, can be spaced. Each step down in pitch multiplies the number of connections per square millimetre and cuts the energy per bit.
| Technology | Typical pitch | Connections per mm² | Used for |
|---|---|---|---|
| Wire bond | ~40–100 µm (edge only) | edge only | Low-cost and memory packages |
| Flip-chip C4 bumps | ~130–150 µm | ~50 | Die to organic substrate |
| Micro-bumps (CoWoS, HBM) | ~25–55 µm | several hundred to ~1,600 | Die to interposer, HBM stacks |
| Hybrid bonding (SoIC, Foveros Direct) | ~10 µm and below | 10,000+ | Die-on-die 3D stacking, cache stacking |
Because the area of a connection shrinks with the square of the pitch, going from 40 µm micro-bumps to 9 µm hybrid bonds gives about 20 times as many connections in the same area, with much shorter, lower-capacitance links.
COWOSThe three flavours of CoWoS
- CoWoS-S: a single large silicon interposer with through-silicon vias. Highest wiring density, but interposer size is limited and silicon is expensive.
- CoWoS-R: an organic redistribution-layer interposer: cheaper and more flexible, with coarser wiring.
- CoWoS-L: an organic interposer with small embedded silicon bridges (local silicon interconnect) only where dense die-to-die wiring is needed. This is how NVIDIA's Blackwell and Rubin and AMD's MI455X reach multi-reticle sizes; TSMC is producing 5.5-reticle versions and plans 14-reticle versions for 2028.
Intel's equivalents are EMIB (embedded silicon bridges in the substrate) and Foveros (face-to-face 3D stacking), combined in products such as Ponte Vecchio, which assembled 47 active tiles.
HBMHow an HBM stack is built
- DRAM wafers are thinned to a few tens of micrometres and drilled with thousands of through-silicon vias (TSVs).
- Dies are stacked 8, 12 or 16 high on a base (logic) die, bonded with micro-bumps and non-conductive film or mass reflow with molded underfill (MR-MUF), and in future with hybrid bonding to fit 16+ dies within the JEDEC height limit.
- The base die handles the physical interface and, from HBM4, can be made on a logic process (Samsung's own 4 nm, SK hynix on TSMC 12 nm), opening the door to custom logic inside the memory stack.
- The stack is placed next to the processor on the interposer; its 2,048-bit HBM4 interface runs at roughly 8–13 Gb/s per pin, giving about 2–3.3 TB/s per stack.
HBM yields compound: one bad die or bond ruins a stack, which is part of why HBM costs several times more per bit than standard DRAM and why supply has constrained AI accelerator shipments.
RELIABILITYWhat can go wrong in a large package
NEXTGlass, panels and optics
Packaging suppliers are developing glass core substrates, which are flatter and more stable than organic cores and allow finer wiring; panel-level packaging, processing large rectangular panels instead of 300 mm wafers to fit more giant packages per run; system-on-wafer (TSMC SoW-X, 40 reticles by 2029); and co-packaged optics, placing optical engines inside the package (TSMC COUPE, production from 2026).